NCP1308DR2G ON Semiconductor, NCP1308DR2G Datasheet - Page 10

• Manufacturer Part Number: NCP1308DR2G
• Description: IC CTRLR PWM CM UVLO HV 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1308DR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 75kHz
• Voltage - Supply: 11 V ~ 20 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 75kHz
• Output Current: 500 mA
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 20 V
• Fall Time: 20 ns
• Rise Time: 40 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1308DR2G; NCP1308DR2GOSTR

Demagnetization Detection
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 17.
further to the driver going-low transition. This prevents the
switching frequency to exceed (1/(T
avoid false leakage inductance tripping at turn-off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
specific component arrangement as detailed by Figure 18.
In this picture, the Zener diodes network protect the IC
against any potential ESD discharge that could appear on
the pins. The first ESD diode connected to the pad, exhibits
a parasitic capacitance. When this parasitic capacitance
(10 pF typically) is combined with R
created and the possibility to switch right in the
drain-source wave exists. This guarantees QR operation
with all the associated benefits (low EMI, no turn-on losses
etc.). R
current flowing through Pin 1 to less than +3 mA / -2 mA:
if during turn-on, the auxiliary winding delivers -30 V (at
the highest line level), then the minimum R
defined by: (-30 + 0.7. This value will be further increased
to introduce a restart delay and also a slight filtering in case
of high leakage energy.
COMPARATOR
TO INTERNAL
The core reset detection is done by monitoring the
-1.0
An internal timer prevents any restart within 10 μs
The NCP1308 demagnetization detection pad features a
7.0
5.0
3.0
1.0
Figure 17. Core Reset Detection is Done through
a Dedicated Auxiliary Winding Monitoring
dem
Figure 18. Internal Pad Implementation
RESTARTS
POSSIBLE
should be calculated to limit the maximum
ESD
0 V
R
esd
ESD
ON
dem
1
4
+ 10 ms)) but also
, a restart delay is
R
50 mV
dem
dem
value is
http://onsemi.com
Aux
NCP1308
10
power.
Overvoltage Protection
comparator and a reference voltage. Figure 20 portrays the
internal arrangement:
superimposed on the V
comparator. When the OVP comparator output goes high,
the NCP1308 fully latches off and stays latched, being
self-supplied by the DSS. The user must unplug the power
supply and wait that the V
voltage of typically 4 V.
Figure 19 portrays a typical Vds shot at nominal output
The overvoltage works by monitoring the V
A 50 ms time-constant filter prevents any parasitic spikes
400
300
200
100
0
V
CC
Figure 20. OVP Section Circuitry
Figure 19. The NCP1308 Operates in
Borderline/Critical Operation
FILTER
50 us
16 V
CC
TO LATCH
CC
to adversely trigger the OVP
-
+
comes down below a reset
+
OVP
COMPARATOR
CC
pin via a