AD650JNZ Analog Devices Inc, AD650JNZ Datasheet - Page 9

• Manufacturer Part Number: AD650JNZ
• Description: IC V-F/F-V CONVERTER 14-DIP
• Manufacturer: Analog Devices Inc
• Type: Volt to Freq & Freq to Voltr

Specifications of AD650JNZ

• Mounting Type: Through Hole
• Frequency - Max: 1MHz
• Full Scale: ±150ppm/°C
• Linearity: ±0.1%
• Package / Case: 14-DIP (0.300", 7.62mm)
• Frequency: 1MHz
• Full Scale Range: 1MHz
• Linearity %: 0.02%
• Supply Voltage Range: ± 9V To ± 18V
• Digital Ic Case Style: DIP
• No. Of Pins: 14
• Ic Generic Number: 650
• Converter Function: VFC/FVC
• Full Scale Frequency: 1000
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (min): ±9V
• Dual Supply Voltage (max): ±18V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: PDIP
• Calibration Error Fs Typ: 5%
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

If the approximate amount of noise that appears on C
(V
inequality:
For example, consider an application calling for a maximum
frequency of 75 kHz, a 0 V to 1 V signal range, and supply
voltages of only ±9 V. The component selection guide of Figure 9
is used to select 2.0 kΩ for R
in a one-shot time period of approximately 7 μs. Substituting
75 kHz into Equation 7 yields a value of 1300 pF for C
the input signal is near zero, 1 mA flows through the integration
capacitor to the switched current sink during the reset phase,
causing the voltage across C
Because the integrator output stage requires approximately 3 V
headroom for proper operation, only 0.5 V margin remains for
integrating extraneous noise on the signal line. A negative noise
pulse at this time could saturate the integrator, causing an error
in signal integration. Increasing C
provides much more noise margin, thereby eliminating this
potential trouble spot.
NOISE
C
), then the value of C
INT
>
+
t
V
OS
S
−
×
3
1
V
×
10
−
V
−
3
NOISE
INT
INT
A
IN
can be checked using the following
to increase by approximately 5.5 V.
and 1000 pF for C
INT
to 1500 pF or 2000 pF
OS
. This results
INT
INT
is known
. When
Rev. D | Page 9 of 20
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100kHz
10kHz
1MHz
1000
100
20
INPUT
RESISTOR
Figure 10. Typical Nonlinearity vs. C
Figure 9. Full-Scale Frequency vs. C
16.9k
40.2k
100k
50
20k
50
100
ONE SHOT CAPACITOR
100
C
OS
C
(pF)
OS
(pF)
1000
1000
OS
OS
INPUT
RESISTOR
16.9k
20k
40.2k
100k
AD650