LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 49

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

7:5
Bit
Once a bit is set in the BMC Error Status registers, it is not automatically cleared by the LM96194 if the error event goes away.
Each bit must be cleared by software. If software attempts to clear a bit while the error condition still exists, and the error is
unmasked, the bit does not clear. If the error is masked, the bit can be cleared even if the error condition still exists.
If the LM96194 is in ASF mode, the BMC Error Status registers are both read-to-clear and write-one-to-clear. When not in ASF
mode, the registers are only write-one-to-clear.
Each register described in this section has a column labeled Sleep Masking. This column describes which error events are masked
in various sleep states. The sleep state of the system is communicated to the LM96194 by writing to the Sleep State Control register.
If a sleep state in this column has a ‘*’ next to it, it denotes that the error event is optionally masked in that sleep mode, depending
on the Sleep State Mask registers.
16.9.1 Register 40h B_Error Status 1
0
1
2
3
4
Register
Address
40h
ZN1_ERR
ZN2_ERR
ZN3_ERR
ZN4_ERR
VRD_ERR
RES
Name
Read/
Write
RWC
RWC This bit is set when any zone 1 temperature has fallen outside its associated
RWC This bit is set when any zone 2 temperature has fallen outside its associated
RWC This bit is set when the zone 3 temperature has fallen outside the zone 3
RWC This bit is set when the zone 4 temperature has fallen outside the zone 4
RWC This bit is set when the VRD_HOT input has been asserted.
R/W
Register
Status 1
R
B_Error
Name
temperature limits.
temperature limits.
temperature limits.
temperature limits.
Reserved
Bit 7
Bit 6
RES
Bit 5
49
Description
_ERR
Bit 4
VRD
ZN4_
Bit 3
ERR
ZN3_
Bit 2
ERR
ZN2_
Bit 1
ERR
ZN1_
Bit 0
ERR
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S3*, S4/5*
S3*, S4/5*
Masking
S3, S4/5
Sleep
none
none
N/A
Default
Value
00h