LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 23

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

12. The master receives byte 1 and then asserts ACK.
13. The master receives byte 2 and then asserts ACK.
14. The master receives N-3 data bytes, and asserts ACK for each one.
15. The master receives data byte N and asserts a NACK.
16. The master asserts a STOP condition to end the transaction.
Special Notes:
1.
2.
3.
4.
14.5.4.4 Simulated SMBus Block-Write Block-Read Process Call
Alternatively, if the master cannot support an SMBus Block-Write Block-Read process call, it can be emulated by two transactions
(a block write followed by a block read). This should only be done in a single master system, since in a dual master system collisions
can occur that corrupt the data and transaction. Below is the sequence of events for these transactions:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The master sends the 7-bit slave address followed by a write bit (low) and the slave asserts the ACK.
11. The master sends the Block Read Command code (F1h) and the slave asserts the ACK.
12. The master sends a repeat START.
13. The master sends the 7-bit slave address followed by a read bit (high) and the slave asserts the ACK.
14. The master receives Byte Count (this matches the size sent by the master in step 7) and asserts the ACK.
15. The master receives Data Byte 1 and asserts the ACK.
16. The master receives Data Byte 2 and asserts the ACK.
17. The master receives N-3 data bytes, and asserts ACK for each one.
18. The master receives the last data byte and asserts a NACK.
19. The master issues a STOP to end this transaction.
The LM96194 returns 00h when address locations outside of normal address space are read.
Block reads do not wrap around from address FFh to 00h
If the master acknowledges more bytes that it requested, the LM96194 continues to supply data until the master does not
acknowledge a byte.
If the master does not acknowledges a byte to prematurely abort a block read, the LM96194 gets off the bus to allow the
master to issue a STOP signal.
The master issues a START to start this transaction.
The master sends the 7-bit slave address followed by a write bit (low).
The slave asserts the ACK.
The master sends the Block Read command code (F1h) and the slave asserts the ACK.
The master sends the Byte Count (2h) for this transaction and the slave asserts the ACK.
The master sends the Start Register Address and the slave asserts the ACK.
The master sends the Byte Count (1-20h) for the Block-Read Process Call and the slave asserts the ACK.
The master sends a STOP to end this transaction.
The master sends a START to start this transaction.
1
S Slave
2
Address
…
W A Block
11
Byte
Count
(1–20h)
(N)
3
4
Read
Comman
d
Code
(F1h)
A
A Byte
12
Data
Byte 1
5
Count
(2h)
A
A Start
13
Data
Byte 2
6
Register
Address
23
A
A Byte
7
Count
(1–20h)
(N)
14
…
15
Data
Byte N
A S Slave
8
15
/A
9
Address
16
P
R A …
10
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