MAX5965BUAX+ Maxim Integrated Products, MAX5965BUAX+ Datasheet - Page 17

• Manufacturer Part Number: MAX5965BUAX+
• Description: IC PSE CTRLR FOR POE 36SSOP
• Manufacturer: Maxim Integrated Products
• Type: Power Over Ethernet Controller (PoE)r

Specifications of MAX5965BUAX+

• Applications: IP Phones, Power over LAN, Network Routers and Switches
• Internal Switch(s): No
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-BSOP (0.300", 7.5mm Width)
• Supply Voltage (max): 60 V
• Supply Voltage (min): 32 V
• Power Dissipation: 1388.9 mW
• Operating Temperature Range: 0 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A valid PD has a 25kΩ discovery signature characteristic
as specified in the IEEE 802.3af/at standard. Table 1
shows the IEEE 802.3af/at specification for a PSE detect-
ing a valid PD signature. See the Typical Operating
Circuits and Figure 1a (Detection, Classification, and
Power-Up Port Sequence). The MAX5965A/MAX5965B
can probe and categorize different types of devices con-
nected to the port such as: a valid PD, an open circuit, a
low resistive load, a high resistive load, a high capacitive
load, a positive DC supply, or a negative DC supply.
During detection, the MAX5965A/MAX5965B keep the
external MOSFET off and force two probe voltages
through the DET_ input. The current through the DET_
input is measured as well as the voltage at OUT_. A
two-point slope measurement is used as specified by
the IEEE 802.3af standard to verify the device connect-
ed to the port. The MAX5965A/MAX5965B implement
appropriate settling times and a 100ms digital integra-
tion to reject 50Hz/60Hz power-line noise coupling.
Table 1. PSE PI Detection Modes Electrical Requirement
(Table 33-2 of the IEEE 802.3af Standard)
Open-Circuit Voltage
Short-Circuit Current
Valid Test Voltage
Voltage Difference
Between Test Points
Time Between Any Two
Test Points
Slew Rate
Accept Signature
Resistance
Reject Signature
Resistance
Open-Circuit Resistance
Accept Signature
Capacitance
Reject Signature
Capacitance
Signature Offset Voltage
Tolerance
Signature Offset Current
Tolerance
High-Power, Quad, Monolithic, PSE Controllers
PARAMETER
______________________________________________________________________________________
SYMBOL
C
ΔV
R
V
V
R
C
R
V
GOOD
VALID
GOOD
V
SLEW
OPEN
I
I
t
BAD
BAD
OS
SC
BP
OC
TEST
OS
< 15
MIN
500
2.8
—
—
19
—
10
1
2
0
0
MAX
26.5
> 33
150
0.1
2.0
30
10
12
—
—
—
—
5
for Power over Ethernet
An external diode, in series with the DET_ input, restricts
PD detection to the first quadrant as specified by the
IEEE 802.3af/at standard. To prevent damage to non-PD
devices, and to protect themselves from an output short
circuit, the MAX5965A/MAX5965B limit the current into
DET_ to less than 2mA maximum during PD detection.
In midspan mode, the MAX5965A/MAX5965B wait 2.2s
before attempting another detection cycle after every
failed detection. The first detection, however, happens
immediately after issuing the detection command.
The CLC_EN bit in register R23h[5] enables the large
capacitor detection feature for legacy PD devices.
When CLC_EN = 1, the high-capacitance detection limit
is extended up to 150µF. CLC_EN = 0 is the default
condition for the normal capacitor size detection. See
Table 1 and the Register Map and Description section.
UNITS
V/µs
mA
ms
kΩ
kΩ
kΩ
µA
nF
µF
V
V
V
V
In detection mode only
In detection mode only
This timing implies a 500Hz maximum probing
frequency
ADDITIONAL INFORMATION
High-Capacitance Detection
17