LTC4251-1IS6#TR Linear Technology, LTC4251-1IS6#TR Datasheet - Page 16

• Manufacturer Part Number: LTC4251-1IS6#TR
• Description: IC CTRLR HOTSWAP NEGVOLT SOT23-6
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4251-1IS6#TR

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: -36 V ~ -72 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-6 Thin, TSOT-23-6
• Family Name: LTC4251-1
• Package Type: TSOT-23
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Height (mm): 0.9mm
• Product Length (mm): 2.9mm
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC4251-1IS6TR; LTC42511IS6TR

APPLICATIONS INFORMATION
is charged by a 230µA current-source pull-up. At time
point 6, the analog current limit loop activates. Between
time point 6 and time point 7, the GATE voltage is held
essentially constant and the sense voltage is regulated at
V
begins to decline. At point 7, the load current falls and
the sense voltage drops below V
limit loop shuts off and the GATE pin ramps further. At
time point 8, the sense voltage drops below V
TIMER now discharges through a 5.8µA current source
pull-down. At time point 9, GATE reaches its maximum
voltage as determined by V
Live Insertion with Short Pin Control of UV/OV
In this example as shown in Figure 8, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4251/
LTC4251-1/LTC4251-2 are activated. At time point 1, the
power pins make contact and V
At time point 2, the UV/OV divider makes contact and
its voltage exceeds V
checks for V
< V
an initial timing cycle starts and the TIMER capacitor
is charged by a 5.8µA current source pull-up. At time
point 3, TIMER reaches the V
tial timing cycle terminates. The TIMER capacitor is then
quickly discharged. At time point 4, the V
is reached and the conditions of GATE < V
SENSE < V
allowed to begin. GATE sources 58µA into the external
MOSFET gate and compensation network. When the
GATE voltage reaches the MOSFET’s threshold, current
begins flowing into the load capacitor. At time point 5, the
SENSE voltage (V
and activates the TIMER. The TIMER capacitor is charged
by a 230µA current source pull-up. At time point 6, the
analog current limit loop activates. Between time point
6 and time point 7, the GATE voltage is held essentially
constant and the sense voltage is regulated at V
the load capacitor nears full charge, its current begins to
LTC4251/LTC4251-1/
LTC4251-2
16
ACL
GATEL
. As the load capacitor nears full charge, its current
and SENSE < V
CB
UVHI
must be satisfied before a start-up cycle is
< UV/OV < V
SENSE
UVHI
– V
CB
. In addition, the internal logic
. When all conditions are met,
EE
IN
.
OVHI
TMRH
) reaches the V
IN
ACL
, TIMER < V
ramps through V
threshold and the ini-
. The analog current
TMRL
CB
TMRL
GATEL
threshold
threshold
ACL
CB
, GATE
LKO
. As
and
and
.
decline. At time point 7, the load current falls and the sense
voltage drops below V
shuts off and the GATE pin ramps further. At time point
8, the sense voltage drops below V
discharges through a 5.8µA current source pull-down.
At time point 9, GATE reaches its maximum voltage as
determined by V
Undervoltage Lockout Timing
In Figure 9, when UV/OV drops below V
TIMER and GATE pull low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV/OV recovers and clears V
an initial time cycle begins followed by a start-up cycle.
Undervoltage Timing with Overvoltage Glitch
In Figure 10, when UV/OV clears V
an initial timing cycle starts. If the system bus voltage
overshoots V
charges. At time point 3, the supply voltage recovers and
drops below the V
restarts followed by a start-up cycle.
Overvoltage Timing
During normal operation, if UV/OV exceeds V
shown at time point 1 of Figure 11, the TIMER status is
unaffected. Nevertheless, GATE pulls down and discon-
nects the load. At time point 2, UV/OV recovers and drops
below the V
If the overvoltage glitch is long enough to deplete the
load capacitor, a full start-up cycle may occur as shown
between time points 3 through 6.
Timer Behavior
In Figure 12a, the TIMER capacitor charges at 230µA if
the SENSE pin exceeds V
if the SENSE pin is less than V
TIMER exceeds V
pull-up and GATE pulls down immediately. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate until it latches.
OVLO
OVHI
IN
threshold. A gate ramp up cycle ensues.
TMRH
OVLO
.
as shown at time point 2, TIMER dis-
, TIMER is latched high by the 5.8µA
ACL
threshold. The initial timing cycle
CB
. The analog current limit loop
. It is discharged with 5.8µA
CB
. In Figure 12b, when
UVHI
UVHI
CB
UVLO
and TIMER now
(time point 1),
(time point 2),
(time point 1),
OVHI
425112fb
as