MAX5936ACESA+ Maxim Integrated Products, MAX5936ACESA+ Datasheet - Page 9

• Manufacturer Part Number: MAX5936ACESA+
• Description: IC HOT-SWAP CTRLR -48V 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5936ACESA+

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: -10 V ~ -80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In a normal power-up GATE cycle, the voltage at V
(referenced to V
breaker threshold voltage, V
GATE voltage is rapidly pulled up to full enhancement.
PGOOD is asserted 1.26ms after GATE is fully enhanced
(see Figure 4). If the voltage at V
of the V
ment), then a power-up to fault management fault has
occurred (see Figure 5). GATE is rapidly pulled to V
turning off the power MOSFET and disconnecting the
load. PGOOD remains deasserted and the MAX5936/
MAX5937 enter the fault management mode.
When the power MOSFET is fully enhanced, the
MAX5936/MAX5937 monitor the drain voltage (V
circuit-breaker and short-circuit faults. The MAX5936/
MAX5937 make use of the power MOSFET’s R
the current-sense resistance to detect excessive current
Figure 4. MAX5936 Normal Condition
Figure 2. GATE Voltage Clamp During Power-Up
CB
(when GATE reaches 90% of full enhance-
C
IN
EE
= 100µF
_______________________________________________________________________________________
) ramps to below 72% of the circuit-
40ms/div
4ms/div
CB
. At this time, the remaining
-48V Hot-Swap Controllers with V
OUT
remains above 72%
Step Immunity and No R
V
50V/div
V
10V/div
V
50V/div
V
50V/div
I
2A/div
IN
V
20V/div
V
1V/div
IN
GATE
OUT
PGOOD
IN
GATE
DS(ON)
OUT
) for
OUT
EE
as
,
through the load. The short-circuit threshold voltage,
V
100mV, 200mV, and 400mV thresholds. V
are temperature-compensated (increasing with tempera-
ture) to track the normalized temperature coefficient of
R
When the load current is increased during full enhance-
ment, this causes V
than V
rejection timer. At the end of the glitch rejection period,
if V
pulled to V
and the part enters fault management. Alternatively,
during full enhancement when V
there is no glitch rejection timer. GATE is immediately
pulled to V
enters fault management.
Figure 3. Load Probe Test During Initial Power-Up
Figure 5. MAX5936 Startup in Fault Condition
SC
DS(ON)
OUT
, is twice V
SC
for typical power MOSFETs.
still exceeds V
, and starts the 1.2ms circuit-breaker glitch
EE
EE
(330ns), PGOOD (PGOOD) is deasserted,
, PGOOD is deasserted, and the part
CB
(V
OUT
SC
40ms/div
to exceed V
= 2 x V
CB
40ms/div
ALL VOLTAGES
REFERENCED TO GND
, the GATE is immediately
CB
) and is available in
OUT
CB
but remains less
V
20V/div
V
20V/div
V
20V/div
exceeds V
EE
LP
OUT
SENSE
CB
V
50V/div
V
10V/div
V
50V/div
V
50V/div
I
2A/div
IN
IN
GATE
OUT
PGOOD
and V
IN
SC
SC
9
,