MAX5936ACESA+ Maxim Integrated Products, MAX5936ACESA+ Datasheet - Page 17

• Manufacturer Part Number: MAX5936ACESA+
• Description: IC HOT-SWAP CTRLR -48V 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5936ACESA+

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: -10 V ~ -80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

load-probe, and V
swap requirement, no decoupling capacitor is recom-
mended for the MAX5936/MAX5937. Because there is
no decoupling capacitor, stray inductance can result in
excessive ringing at the GND pin during power-up or
during very rapid V
in every application design since ringing at the GND
pin may exceed the absolute maximum supply rating
for the part.
Figure 15. MAX5936/MAX5937 Slew Rate vs. C
Figure 16. Adjusting the MAX5936/MAX5937 Slew Rate
-48V
GND
0.01
0.1
10
GND
1
V
EE
0.1
MAX5936
MAX5937
EE
______________________________________________________________________________________
IN
GATE
. Because of the nature of the hot-
SLEW RATE vs. C
1
V
steps. This should be examined
OUT
R
GATE
C
SLEW
10
C
SLEW
(nF)
-48V Hot-Swap Controllers with V
SLEW
100
C
SLEW
LOAD
1000
Step Immunity and No R
LOAD
During hot plug-in/unplug and fast V
inductance in the power path can cause voltage ring-
ing above the normal input DC value, which may
exceed the absolute maximum supply rating. An input
transient such as that caused by lightning can also put
a severe transient peak voltage on the input rail. The
following techniques are recommended to reduce the
effect of transients:
1) Minimize stray inductance in the power path using
2) Add a high-frequency (ceramic) bypass capacitor
3) Add a 1kΩ resistor in series with the MAX5936/
The power-up GATE cycle and the step GATE cycle are
quite similar but have distinct differences. Understanding
these differences may clarify application issues.
The power-up GATE cycle occurs during the initial
power-up of the MAX5936/MAX5937 and the associat-
ed power MOSFET and load. The power-up GATE
cycle can result in full enhancement or in a fault (all
voltages are relative to V
Power-Up to Full Enhancement:
1) At the beginning of the power-up sequence to the
2) When GATE reaches the gate threshold voltage of
3) When V
wide traces and minimize loop area including the
power traces and the return ground path.
on the backplane as close as possible to the plug-
in connector (Figure 17).
MAX5937’s GND pin and a 0.1µF capacitor from
GND to V
start of the power-up GATE cycle, the GATE is held
at V
load-probe test, GATE is held at V
tional 350µs and then is allowed to float for 650µs.
At this point, the GATE begins to ramp with 52µA
charging the gate of the power MOSFET. [GATE
turn-on]
the power MOSFET, V
toward V
rapidly pulled to full enhancement and the power-
up GATE cycle is complete. 1.26ms after GATE is
pulled to full enhancement, PGOOD will assert. [Full
enhancement]
EE
. Following a successful completion of the
OUT
EE
EE
. [V
to limit transient current going into this pin.
ramps below 72% V
OUT
Input Transient Protection
ramp]
GATE Cycle During Power-Up
EE
).
OUT
begins to ramp down
Appendix A
CB
GATE Cycles
IN
EE
, the GATE is
SENSE
steps, stray
for an addi-
IN
17