MAX5936ACESA+ Maxim Integrated Products, MAX5936ACESA+ Datasheet - Page 18

• Manufacturer Part Number: MAX5936ACESA+
• Description: IC HOT-SWAP CTRLR -48V 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Hot-Swap Controllerr

Specifications of MAX5936ACESA+

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: -10 V ~ -80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

-48V Hot-Swap Controllers with V
Step Immunity and No R
Power-Up to Fault Management:
1) Same as step 1 above. [GATE turn-on]
2) Same as step 2 above. [V
3) GATE ramps to 90% of full enhancement while
A step GATE cycle occurs only after a successful
power-up GATE cycle to full enhancement occurs and
as a result of a positive V
relative to V
Step to Full Enhancement:
1) A V
2) After a step is detected, V
3) Following the 350µs of GATE pulldown, GATE is
18
Figure 17. Protecting the MAX5936/MAX5937 Input from High-
Voltage Transients
1µF
V
GATE is rapidly pulled to V
ment is initiated. [Fault management]
above STEP
detection]
response to the step. When V
GATE is immediately pulled to V
the power MOSFET. GATE is held at V
dampen any ringing. Once GATE is pulled to V
the gate cycle has begun and STEP_MON can safely
drop below STEP
step GATE cycle to full enhancement without initiat-
ing fault management. [GATE pulldown]
allowed to float for 650µs. At this point, the GATE
______________________________________________________________________________________
OUT
BACKPLANE
IN
48V ±10%
0.1µF
remains above 72% V
step occurs resulting in STEP_MON rising
EE
).
TH
before V
TH
TVS
68V
GATE Cycle During V
and successfully complete a
OUT
IN
OUT
OUT
step (all voltages are
rises above V
CB
EE
PLUG-IN CARD
OUT
ramp]
EE
, at which point the
GND
and fault manage-
rises above V
V
EE
, rapidly turning off
rises above V
PGOOD
1kΩ
EE
for 350µs to
SC
IN
100kΩ
. [Step
SC
Step
SC
EE
in
,
,
SENSE
4) When GATE reaches the gate threshold voltage of
5) When V
Step to Fault Management:
1) Same as step 1 above. [Step detection]
2) Same as step 2 above. [GATE pulldown]
3) Same as step 3 above. [GATE turn-on]
4) Same as step 4 above. [VOUT ramp]
5) If STEP_MON is below STEP
It should be emphasized that while STEP_MON remains
above STEP
blocked. During this time it is possible for there to be
multiple events involving V
those falling below 75% V
when V
ed where GATE is first pulled low then allowed to ramp
up. Then finally, when V
be fully enhanced.
begins to ramp with 52µA charging the gate of the
power MOSFET. [GATE turn-on]
the power MOSFET, V
toward the new lower V
GATE is below the MOSFET threshold, the MOSFET
is off and V
time constant of the load. [V
rapidly to full enhancement and the step GATE
cycle is complete. If STEP_MON remains above
STEP
enhancement and V
V
full enhancement. In this condition, if V
below 72% of V
STEP
and the step GATE cycle is complete. PGOOD
remains asserted throughout the step GATE cycle.
[Full enhancement]
to 90% of full enhancement and V
above 72% V
Fault management is initiated and PGOOD is de-
asserted. If STEP_MON is above STEP
GATE ramps to 90% of full enhancement and V
remains above 72% of V
It will not be pulled to full enhancement nor will it be
pulled to V
72% of V
STEP
and a fault is avoided. Conversely, if STEP_MON
drops below STEP
pulled to V
PGOOD is deasserted. [Fault management]
CB
OUT
, GATE remains at 90% and will not be pulled to
TH
TH
TH
OUT
, GATE is rapidly pulled to full enhancement
, GATE is rapidly pulled to full enhancement
rises above V
when GATE has ramped to 90% of full
TH
EE
CB
EE
OUT
ramps below 72% V
. In this condition, if V
, fault management is initiated, and
the current fault management is
CB,
before STEP_MON drops below
CB
IN
will droop depending on the RC
GATE is rapidly pulled to V
before STEP_MON drops below
TH
OUT
SC
OUT
CB
OUT
OUT
first, the GATE is rapidly
, a full GATE cycle is initiat-
CB
EE
. In each of these events,
conditions are met, it will
remains above 72% of
, GATE remains at 90%.
OUT
. In the interval where
begins to ramp down
rising above V
TH
ramp]
when GATE ramps
CB
OUT
, the GATE pulls
OUT
drops below
OUT
TH
remains
SC
drops
when
then
OUT
EE
.