STPM11ATR STMicroelectronics, STPM11ATR Datasheet - Page 27

• Manufacturer Part Number: STPM11ATR
• Description: IC ENERGY METER 1 PHASE 20TSSOP
• Manufacturer: STMicroelectronics

Specifications of STPM11ATR

• Input Impedance: 100 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 1.5V
• Voltage - I/o Low: 0.8V
• Current - Supply: 4.7mA
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Meter Type: Single Phase
• Output Voltage: +/- 0.4 V
• Output Current: 150 mA
• Input Voltage: 3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5984-2

STPM11, STPM12, STPM13, STPM14
Table 15.
000000
000001
000011
000101
000110
binary
6-BIT
Address
DEC
6
0
1
3
5
(1)
The very first CFG bit, called TSTD, is used to disable any change of system signals after it
has been permanently set. During the configuration phase, each bit set to logic level 1
increases the supply current of STPM01 of about 120 µA, until the TSTD bit is set to 1. The
residual increase of supply current is 2 µA per each bit set to 1. It is then recommended to
set the TSTD bit to 1 after the configuration procedure in order to keep the supply current as
low as possible.
The STPM1x can work either using the data stored in the OTP cells or the data available in
the shadow latches. This can be chosen according to the value RD Mode signal (see
paragraph
OTP shadow latches. If the RD is cleared, the CFG bits originates from corresponding OTP
antifuses. In this way, it is possible to temporarily set up certain configurations or calibrations
of the device then verify and change, if necessary. This exercise is extensively used during
production tests.
Each configuration bit can be written sending a byte command to STPM1x through its
configuration interface. The procedure to write the configuration bits is described in the
Configuration Interface section (7.17).
After the TSTD bit has been set, no other command can be sent to the STPM1x. This
implies that the shadow latches can no longer be used as source of configuration data.
Configuration bits map
Name
TSTD
MDIV
APL
PST
7.16
N. of
bits
1
1
1
2
for description). If the RD is set, the CFG bits originates from corresponding
Test mode and OTP write disable:
- TSTD=0: testing and continuous pre-charge of OTP when in read mode,
- TSTD=1:normal operation and no more writes to OTP
Measurement frequency range selection:
- MDIV=0: 4.000MHz to 4.194MHz,
- MDIV=1: 8.000MHz to 8.192MHz
LED pin frequency output:
- APL=0: P
- APL=1:
KMOT=0
KMOT=1
KMOT=2
KMOT=3
Current channel sensor type, gain and tamper selection:
STPM11/12
- PST=0: primary is Rogowsky coil x8 (x16 if ADDG=1)
- PST=1: primary is Rogowsky coil x24 (x32 if ADDG=1),
- PST=2: primary is CT x8,
- PST=3: primary is shunt x32,
STPM13/14
- PST=0: primary is Rogowsky coil x8 (x16 if ADDG=1), secondary is
Rogowsky coil x8 (x16 if ADDG=1),
- PST=1: primary is Rogowsky coil x24 (x32 if ADDG=1), secondary is
Rogowsky coil x24 (x32 if ADDG=1),
- PST=2: primary is CT x8, secondary is CT x8
- PST=3: primary is CT x8, secondary is shunt x32
→
→
→
→
Doc ID 13167 Rev 7
P/64
P/128
P/32
P/256
Description
(1)
Theory of operation
27/46