ISL6295CVZ Intersil, ISL6295CVZ Datasheet - Page 20

• Manufacturer Part Number: ISL6295CVZ
• Description: IC FUEL GAUGE LOW VOLTAGE8-TSSOP
• Manufacturer: Intersil

Specifications of ISL6295CVZ

• Function: Fuel, Gas Gauge/Monitor
• Battery Type: Lithium-Ion (Li-Ion), Lithium-Polymer (Li-Pol)
• Voltage - Supply: 2.8 V ~ 7 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Battery Management Function: Fuel Gauge
• Supply Voltage Range: 2.8V To 7V
• Interface Type: 2-Wire, Serial, I2C
• Battery Ic Case Style: TSSOP
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATION MODE CONTROL REGISTER - OPmode
(Address 7A Hex/122 Decimal)
SSLP
Reserved Reserved bit.
SSLPdiv
SHELF
POR
sPOR
SSLP
7
RESERVED
Sample-Sleep Mode enable: Setting this bit to
‘1’ immediately enables Sample-Sleep Mode.
Clearing this bit immediately disables Sample-
Sleep mode.
Sample-Sleep Divider setting: Sets the interval
between executing an A/D conversion cycle
during Sample-Sleep mode. The time interval
between each conversion cycle is defined by:
2^(SampDiv) * 2^(SSLPdiv) * 0.5 sec
Note that if the time taken to complete an A/D
conversion cycle is more than the defined
interval, the time-overlapped pending
conversion cycle(s) will be skipped until the
previous conversion cycle is complete.
Shelf-Sleep Mode enable: Setting this bit to ‘1’
will prepare the device for Shelf-Sleep mode. The
Shelf- Sleep mode will not be entered until a
SMBus Stop condition occurs, when both SDA
and SCL pins go low.
Power-on Reset Flag: This bit will read a ‘1’
when a Power-on Reset has occurred. Writing a
‘0’ to this bit will clear the POR flag.
Soft Reset: Writing a ‘1’ to this bit will cause the
device to re-initialize by reloading EEPROM
contents into all working registers. This function
has the same effect as the initial Power-on
Reset.
6
5
SSLPdiv
4
20
3
SHELF
2
POR
1
sPOR
0
ISL6295
TRIP CONTROL REGISTER - TRIPctrl
(Address 76 Hex/118 Decimal)
Iex
Note1
Ient
VPex
Note1
VPent
GPADent Enter Sample-Sleep Mode on GPAD voltage: A
Shent
Rsvd
Oflow
Note1: The exit conditions are verifyed by design but not
tested in production.
lex
7
lent
6
Exit from Sample-Sleep Mode on current: A ‘1’ in
this bit will enable an exit from Sample-Sleep
Mode upon the following condition: |current|
>I+Trip
Enter Sample-Sleep Mode on current: A ‘1’ in
this bit will enable entry to Sample-Sleep Mode
under the following condition: | current | <I-Trip
Exit from Sample-Sleep Mode on Pack voltage:
A ‘1’ in this bit will enable an exit from Sample-
Sleep Mode upon the following condition: VP >
VPtrip
Enter Sample-Sleep Mode on Pack voltage:
(Use VPent only if GPAD is not used and
grouned) A ‘1’ in this bit will enable entry to
Sample-Sleep Mode upon the following
condition: VP < VCtrip
‘1’ in this bit will enable entry to Sample-Sleep
Mode upon the following condition: GPAD <
VCtrip
Enter Shelf-Sleep Mode on Pack voltage: A ‘1’
in this bit will enable entry to Shelf-Sleep mode
upon the following condition: VP < SStrip
Reserved bit.
ADC Overflow flag: This bit is set when the ADC
input voltage is beyond the designed voltage
range of the ADC. This bit will remain set until a
‘0’ is written to it.
VPex
5
VPent GPADent Shent
4
3
2
Rsvd Oflow
February 8, 2011
1
FN9074.2
0