AT49BV320-11TI Atmel, AT49BV320-11TI Datasheet - Page 6

• Manufacturer Part Number: AT49BV320-11TI
• Description: IC FLASH 32MBIT 110NS 48TSOP
• Manufacturer: Atmel

Specifications of AT49BV320-11TI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 110ns
• Interface: Parallel
• Voltage - Supply: 2.65 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6
AT49BV/LV320(T)/321(T)
VPP PIN: The circuitry of the AT49BV/LV32X(T) is designed so that the device cannot be pro-
grammed or erased if the V
program and erase operations can be performed. The V
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 11
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the AT49BV/LV32X(T) contains a programmable configuration register.
The configuration register allows the user to specify the status bit operation. The configuration
register can be set to one of two different values, “00” or “01”. If the configuration register is set
to “00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be
given after a successful program or erase operation before the part will return to the read
mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit command to
return the device to read mode. The default value (after power-up) for the configuration regis-
ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the
“Command Definition in Hex” table on page 12, the value of the configuration register can be
changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-
ter. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
DATA POLLING: The AT49BV/LV32X(T) features Data Polling to indicate the end of a pro-
gram cycle. If the status configuration register is set to a “00”, during a program cycle an
attempted read of the last byte/word loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. During a chip or sector erase operation, an attempt to read the device
will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read
from the device. Data Polling may begin at any time during the program cycle. Please see
“Status Bit Table” on page 11 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has com-
pleted a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and V
bit as shown in the algorithm in Figures 1 and 2 on page 9.
TOGGLE BIT: In addition to Data Polling the AT49BV/LV32X(T) provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the memory will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle. Please see “Sta-
tus Bit Table” on page 11 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and V
bit as shown in the algorithm in Figures 3 and 4 on page 10.
ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates
whether the program or erase operation has exceeded a specified internal pulse count limit. If
the status bit is a “1”, the device is unable to verify that an erase or a byte/word program oper-
ation has been successfully performed. The device may also output a “1” on I/O5 if the system
tries to program a “1” to a location that was previously programmed to a “0”. Only an erase
operation can change a “0” back to a “1”. If a program (Sector Erase) command is issued to a
protected sector, the protected sector will not be programmed (erased). The device will go to a
status read mode and the I/O5 status bit will be set high, indicating the program (erase) opera-
tion did not complete as requested. Once the erase/program status bit has been set to a “1”,
PP
voltage is less that 0.8V. When V
pp
pin cannot be left floating.
PP
is at 1.65V or above, normal
1494H–FLASH–01/03
PP
PP
status
status