IDT70V9289L9PFI IDT, Integrated Device Technology Inc, IDT70V9289L9PFI Datasheet - Page 12

IC SRAM 1MBIT 9NS 100TQFP

IDT70V9289L9PFI

Manufacturer Part Number
IDT70V9289L9PFI
Description
IC SRAM 1MBIT 9NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V9289L9PFI

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
1M (64K x 16)
Speed
9ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Density
1Mb
Access Time (max)
20ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
40MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
32b
Package Type
TQFP
Operating Temp Range
-40C to 85C
Number Of Ports
2
Supply Current
240mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Word Size
16b
Number Of Words
64K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70V9289L9PFI
800-1401

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V9289L9PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Timing Waveform of a Bank Select Pipelined Read
Timing Waveform with Port-to-Port Flow-Through Read
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9389 or IDT70V9289 for this waveform, and are setup for depth expansion
2. UB, LB, OE, and ADS = V
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE
5. OE = V
6. If t
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
in this example. ADDRESS
If t
CCS
CCS
0
, UB, LB, and ADS = V
< maximum specified, then data from right port READ is not valid until the maximum specified for t
> maximum specified, then data from right port READ is not valid until t
ADDRESS
ADDRESS
IL
ADDRESS
ADDRESS
DATA
DATA
DATA
for the Right Port, which is being read from. OE = V
DATA
CE
CE
CLK
R/W
CLK
R/W
OUT(B1)
OUT(B2)
OUT "B"
CLK
0(B1)
0(B2)
IN "A"
(B1)
(B2)
"A"
"A"
"A"
"B"
"B"
"B"
(B1)
IL
IL
; CE
; CE
t
t
t
t
= ADDRESS
SC
SC
SA
SA
1(B1)
1
A
A
, CNTEN, and CNTRST = V
0
0
t
t
t
t
HC
HC
, CE
MATCH
HA
HA
t
t
t
VALID
t
SA
SD
SW
CH2
MATCH
1(B2)
t
t
SA
SW
t
CYC2
t
t
t
(B2)
HW
HA
HD
t
, R/W, CNTEN, and CNTRST = V
DC
t
in this situation.
t
t
CL2
HW
HA
A
A
t
CCS
1
1
(6)
t
t
CWDD
CD2
IH
IH
t
CD1
.
for the Left Port, which is being written to.
(6)
t
t
SC
SC
Q
A
A
2
0
2
t
t
t
DC
HC
HC
6.42
12
CCS
t
IH
CD2
.
+ t
CD1
. t
CWDD
Q
A
A
3
3
1
VALID
t
t
DC
t
CKHZ
CKLZ
does not apply in this case.
MATCH
t
CD2
(3)
(3)
NO
MATCH
Industrial & Commercial Temperature Ranges
NO
CWDD
(1,2)
A
A
Q
.
4
4
2
t
t
CKLZ
CKHZ
t
t
DC
CD2
(3)
t
(3)
CD1
(4,5,7)
A
A
Q
5
5
3
t
t
CKHZ
CKLZ
t
CD2
(3)
(3)
4856 drw 08
VALID
4856 drw 09
A
A
Q
6
6
4

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