NAND04GW3B2DN6E NUMONYX, NAND04GW3B2DN6E Datasheet - Page 19

• Manufacturer Part Number: NAND04GW3B2DN6E
• Description: IC FLASH 4GBIT 48TSOP
• Manufacturer: NUMONYX

Specifications of NAND04GW3B2DN6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 4G (512M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NAND04G-B2D, NAND08G-BxC
4.5
4.6
If the Read Enable pulse frequency is lower then 33 MHz (t
output data is latched on the rising edge of Read Enable signal (see
For higher frequencies (t
used. In this mode, data output bus operations are valid on the input/output bus for a time of
t
See
Write protect
Write protect bus operations protect the memory against program or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operations, and, therefore, the contents of the memory array cannot be altered. The Write
Protect signal is not latched by Write Enable to ensure protection, even during power-up.
Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled, and power consumption is reduced.
Table 5.
1. Only for x16 devices.
2. WP must be V
Table 6.
1. Any additional address input cycles are ignored.
2. A30 is only valid for the NAND08G-BxC devices.
RLQX
Command input
Bus operation
cycle
Address input
Write protect
Data output
Bus
Data input
2
3
1
4
5
Standby
nd
Table 31
rd
th
th
st
after the falling edge of Read Enable signal (see
(1)
Bus operations
Address insertion (x8 devices)
I/O7
A19
A27
V
V
A7
for details on the timings requirements.
IH
IL
IL
when issuing a Program or Erase command.
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
I/O6
A18
A26
V
V
A6
V
AL
V
V
V
RLRL
X
X
IL
IL
IH
IL
IL
IL
lower than 30 ns), the EDO (extended data out) mode must be
V
CL
V
V
V
X
X
IH
IL
IL
IL
I/O5
A17
A25
V
V
A5
IL
IL
Falling
V
V
V
R
X
X
IH
IH
IH
I/O4
A16
A24
V
V
A4
Rising
Rising
Rising
IL
IL
V
W
X
X
IH
I/O3
A11
A15
A23
V
V
A3
Figure
IL
IL
WP
X
V
V
/V
X
X
(2)
IH
IL
DD
RLRL
28).
A30
I/O2
A10
A14
A22
higher than 30 ns), the
A2
Data output
I/O0 - I/O7
Command
Data input
Address
(2)
Figure
X
X
I/O1
A13
A21
A29
A1
A9
Bus operations
27).
I/O8 - I/O15
Data output
Data input
X
X
X
X
I/O0
A12
A20
A28
A0
A8
19/72
(1)