CY7C131-55JXC Cypress Semiconductor Corp, CY7C131-55JXC Datasheet - Page 9

IC SRAM 8KBIT 55NS 52PLCC

CY7C131-55JXC

Manufacturer Part Number
CY7C131-55JXC
Description
IC SRAM 8KBIT 55NS 52PLCC
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr
Datasheet

Specifications of CY7C131-55JXC

Memory Size
8K (1K x 8)
Package / Case
52-PLCC
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Access Time
55 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Current
110 mA
Organization
1 K x 8
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
2
Operating Supply Voltage
5 V
Density
8Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
20b
Package Type
PLCC
Operating Temp Range
0C to 70C
Supply Current
110mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
8b
Number Of Words
1K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1791
CY7C131-55JXC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C131-55JXC
Manufacturer:
LATTICE
Quantity:
539
Part Number:
CY7C131-55JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C131-55JXCT
Manufacturer:
CYPRESS
Quantity:
924
Part Number:
CY7C131-55JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Notes
Document #: 38-06002 Rev. *E
20. R/W is HIGH for read cycle.
21. Device is continuously selected, CE = V
22. Address valid prior to or coincident with CE transition LOW.
DATA OUT
DATA OUT
ADDRESS
ADDRESS
ADDRESS
I
OE
I
DOUT
CE
BUSY
CC
SB
R/W
D
INR
R
L
L
R
L
PREVIOUS DATA VALID
t
PU
t
LZCE
t
OHA
IL
t
LZOE
and OE = V
Read with BUSY, Master: CY7C130 and CY7C131
t
t
PS
ACE
IL
.
Figure 5. Read Cycle No. 1
Figure 6. Read Cycle No. 2
Figure 7. Read Cycle No. 3
t
Either Port CE/OE Access
DOE
Either Port Address Access
t
BLA
t
ADDRESS MATCH
AA
t
RC
t
RC
t
PWE
ADDRESS MATCH
DATA VALID
[20, 21]
[20, 22]
[21]
t
WDD
VALID
t
HZOE
t
DDD
DATA VALID
t
BHA
t
CY7C130, CY7C130A
CY7C131, CY7C131A
HD
CY7C140, CY7C141
t
HZCE
t
PD
t
BDD
VALID
Page 9 of 19
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