CY7C131-55JXC Cypress Semiconductor Corp, CY7C131-55JXC Datasheet - Page 6

• Manufacturer Part Number: CY7C131-55JXC
• Description: IC SRAM 8KBIT 55NS 52PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C131-55JXC

• Memory Size: 8K (1K x 8)
• Package / Case: 52-PLCC
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 110 mA
• Organization: 1 K x 8
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 5 V
• Density: 8Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 20b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Supply Current: 110mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 52
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1791; CY7C131-55JXC

Switching Characteristics
Document #: 38-06002 Rev. *E
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Shaded areas contain preliminary information.
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
12. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
13. AC Test Conditions use V
14. At any given temperature and voltage condition for any given device, t
15. t
16. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
Read Cycle
Write Cycle
Parameter
I
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
LZCE
/I
OH,
, t
LZWE
and 30 pF load capacitance.
, t
[16]
HZOE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
R/W Pulse Width
Data Setup to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
, t
LZOE
, t
OH
HZCE
= 1.6V and V
and t
HZWE
Description
[10, 14, 15]
[10, 14, 15]
[15]
[15]
[10, 14, 15]
[10, 14, 15]
OL
Over the Operating Range
are tested with C
[13]
[10]
[13]
[13]
= 1.4V.
[10]
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
HZCE
is less than t
[7, 12]
Min
7C131-15
15
15
12
12
12
10
7C131A-15
0
3
3
0
2
0
0
0
7C141-15
LZCE
Max
and t
15
15
10
10
10
15
10
[4]
HZOE
is less than t
Min
7C130-25
25
25
20
20
15
15
0
3
5
0
2
0
0
0
7C131-25
7C140-25
7C141-25
LZOE
Max
25
25
15
15
15
25
15
CY7C130, CY7C130A
CY7C131, CY7C131A
[4]
.
CY7C140, CY7C141
Min
7C130A-30
30
30
25
25
25
15
0
3
5
0
2
0
0
0
7C130-30
7C131-30
7C140-30
7C141-30
Max
30
30
20
15
15
25
15
Page 6 of 19
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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