MCIMX6Q6AVT10AC Freescale Semiconductor, MCIMX6Q6AVT10AC Datasheet - Page 6

• Manufacturer Part Number: MCIMX6Q6AVT10AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q6AVT10AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

Introduction
The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers:
1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus
throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the
ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE).
6
•
•
•
•
•
•
•
•
•
USB
— One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
— Three USB 2.0 (480 Mbps) hosts:
Expansion PCI Express port (PCIe) v2.0 one lane
— PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint
Miscellaneous IPs and interfaces:
— Three I2S/SSI/AC97, up to 1.4 Mbps each
— Enhanced Serial Audio Interface (ESAI), up to 1.4 Mbps per channel
— Five UARTs, up to 4.0 Mbps each:
— Five eCSPI (Enhanced CSPI)
— Three I2C, supporting 400 kbps
— Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/1000
— Four Pulse Width Modulators (PWM)
— System JTAG Controller (SJC)
— GPIO with interrupt capabilities
— 8x8 Key Pad Port (KPP)
— Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx
— Two Controller Area Network (FlexCAN), 1 Mbps each
— Two Watchdog timers (WDOG)
— Audio MUX (AUDMUX)
— MLB (MediaLB) provides interface to MOST Networks (150 Mbps) with the option of DTCP
Provide PMU, including LDO supplies, for on-chip resources
Use Temperature Sensor for monitoring the die temperature
Support DVFS techniques for low power modes
Use Software State Retention and Power Gating for ARM and MPE
Support various levels of system power modes
Use flexible clock gating control scheme
– One HS host with integrated High Speed PHY
– Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) PHY
operations. Uses x1 PHY configuration.
– Providing RS232 interface
– Supporting 9-bit RS485 multidrop mode
– One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is
cipher accelerator
:
due to the SoC IOMUX limitation, since all UART IPs are identical.
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
1
Mbps
Freescale Semiconductor