MCIMX6Q6AVT10AC Freescale Semiconductor, MCIMX6Q6AVT10AC Datasheet - Page 44

• Manufacturer Part Number: MCIMX6Q6AVT10AC
• Description: Processors - Application Specialized i.MX6Q
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6Q6AVT10AC

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 16 KB
• Operating Supply Voltage: 1.05 V to 1.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FCBGA
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 2

1
2
Electrical Characteristics
A 4-stage pipeline is utilized in the MLB 6-pin implementation in order to facilitate design, maximize
throughput, and allow for reasonable PCB trace lengths. Each cycle is one ipp_clk_in* (internal clock
from MLB PLL) clock period. Cycles 2, 3, and 4 are MLB PHY related. Cycle 2 includes clock-to-output
delay of Signal/Data sampling flip-flop and Transmitter, Cycle 3 includes clock-to-output delay of
Signal/Data clocked receiver, Cycle 4 includes clock-to-output delay of Signal/Data sampling flip-flop.
MLB 6-pin pipeline diagram is shown in
Table 33
44
Differential pulse skew
Transition Low to High Time
Transition High to Low Time
MLB external clock Operating Frequency
MLB PLL clock Operating Frequency
t
the negative going edge of the same channel.
Measurement levels are 20-80% from output voltage.
SKD
= | t
PHLD
shows the AC parameters for MLB I/O.
– t
PLHD
i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2
1
VDIFF
|, is the magnitude difference in differential propagation delay time between the positive going edge and
Parameter
padn
padp
Figure 7. Differential MLB Driver Transition Time Waveform
2
20%
Table 33. I/O AC Parameters of MLB PHY
Figure 8. MLB 6-Pin Pipeline Diagram
Figure
0V (Differential)
t
VDIFF = {padp} - {padn}
TLH
80%
0V
8.
Symbol Test Condition
fclk_ext
fclk_pll
t
t
t
SKD
TLH
THL
80%
between padP
Rload = 50 
and padN
—
—
0V
0V
t
THL
20%
Min
—
—
—
—
—
V
V
OH
OL
Freescale Semiconductor
Typ
—
—
—
—
—
102.4
307.2
Max
0.1
1
1
MHz
MHz
Unit
ns