DS32512W Maxim Integrated, DS32512W Datasheet - Page 90

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Bit Error Count (BEC[23:16])
Bit Error Count (BEC[23:0]). This field is the holding register for an internal BERT bit error counter that tracks the
number of bit errors detected in the incoming data stream since the last performance monitoring update. The
internal counter stops incrementing when it reaches a count of FF FFFFh and does not increment when an OOS
condition exists. This register is updated when a performance monitoring update is performed. See Section 8.7.4.
The source for the performance monitoring update signal is specified by the BERT.CR:PMUM bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Bit Count (BC[15:0])
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: Bit Count (BC[31:16])
Bit Count (BC[31:0]). This field is the holding register for an internal BERT bit counter that tracks the total number
of bit received in the incoming data stream since the last performance monitoring update. The internal counter
stops incrementing when it reaches a count of FFFF FFFFh and does not increment when an OOS condition
exists. This register is updated when a performance monitoring update is performed. See Section 8.7.4. The
source for the performance monitoring update signal is specified by the BERT.CR:PMUM bit.
15
15
15
—
0
7
0
0
7
0
0
7
0
14
14
14
—
0
6
0
0
6
0
0
6
0
BERT.RBECR2
BERT Receive Bit Error Count Register #2
n * 80h + 66h
BERT.RBCR1
BERT Receive Bit Count Register #1
n * 80h + 68h
BERT.RBCR2
BERT Receive Bit Count Register #2
n * 80h + 6Ah
13
—
13
13
0
5
0
0
5
0
0
5
0
90 of 130
12
—
12
12
0
4
0
0
4
0
0
4
0
BEC[23:16]
BC[31:24]
BC[23:16]
BC[15:8]
BC[7:0]
11
11
11
—
0
3
0
0
3
0
0
3
0
10
10
10
—
0
2
0
0
2
0
0
2
0
DS32506/DS32508/DS32512
—
9
0
1
0
9
0
1
0
9
0
1
0
—
8
0
0
0
8
0
0
0
8
0
0
0