DS32512W Maxim Integrated, DS32512W Datasheet - Page 42

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

8.7.3 General-Purpose I/O Pins
When a microprocessor interface is enabled
available per port, each of which can be used as a general-purpose input, general-purpose output, or loss-of-signal
output. In addition, GPIOB1, GPIOB2, and GPIOB3 can be used as a global I/O signal. The GPIO pins are
independently configurable using the GPIO yn S fields of the
(see
GLOBAL.GIOBRR
state of the LINE.RSR:LOS status bit. When a port is powered down and a GPIO pin has been programmed as an
associated loss-of-signal output, the pin is held low. Programming a GPIO pin as a global signal overrides the I/O
settings specified by the GPIOynS field for that pin and configures the pin as an input or an output as shown in
Table
Table 8-14. GPIO Pin Global Signal Assignments
Note: n = 1 to 12, k = 4 to 12.
Table 8-15. GPIO Pin Control
Note: n = 1 to 12, y = A or B.
8.7.4 Performance Monitor Register Update
Each performance monitor counter can count at least one second of events before saturating at the maximum
count. Each counter has an associated status bit that is set when the counter value is not zero, a latched status bit
that is set when the counter value changes from zero to one, and a latched status bit that is set each time the
counter is incremented.
There is a holding register for each performance monitor counter that is updated when a performance monitoring
update is performed. A performance monitoring update causes the counter value to be loaded into the holding
register and the counter to be cleared. If a counter increment occurs at the exact same time as the counter reset,
the counter is loaded with a value of one, and the “counter is non-zero” latched status bit is set.
The performance monitor update (PMU) signal initiates a performance monitoring update. The PMU signal can be
sourced from a general-purpose I/O pin (GPIOB1), the internal one-second reference, a global register bit
(GLOBAL.CR1:GPMU), or a port register bit (PORT.CR1:PMU). Note: The BERT PMU can be sourced from a
block level register bit (BERT.CR:LPMU). To use GPIOB1, GLOBAL.CR1.GPM[1:0] is set to 01, the appropriate
PORT.CR1:PMUM bits are set to 1, and the appropriate BERT.CR:PMUM bits are set to 1. To use the internal one-
second reference, GLOBAL.CR1:GPM[1:0] is set to 1X, the appropriate PORT.CR1:PMUM bits are set to 1, and
the appropriate BERT.CR:PMUM bits are set to 1. To use the global PMU register bit, GLOBAL.CR1:GPM[1:0] is
set to 00, the appropriate PORT.CR1:PMUM bits are set to 1, and the appropriate BERT.CR:PMUM bits are set to
1. To use the port PMU register bit, the associated PORT.CR1:PMUM bit is set to 0, and the appropriate
BERT.CR:PMUM bits are set to 1. To use the BERT.CR:LPMU register bit, the appropriate BERT.CR:PMUM bit is
set to 0.
When using the global or port PMU register bits, the PMU bit should be set to initiate the process and cleared when
the associated PMS status bit (GLOBAL.SR:GPMS or PORT.SR:PMS) is set. When using the GPIO pin or internal
one-second reference, the PMS bit is set shortly after the signal goes high, and cleared shortly after the signal
GPIOynS[1:0]
GPIOA n
GPIOB1
GPIOB2
GPIOB3
GPIOB k
PIN
Table
8-14.
00
01
10
11
8-15). When a GPIO pin is configured as an input, its value can be read from the
None
Global PMU input
Global TMEI input
1SREF output
None
registers. When a GPIO pins is configured as a loss-of-signal status output, its state mimics the
FUNCTION
Input
Output LOS status for port n
Output logic 0
Output logic 1
FUNCTION
GLOBAL SIGNAL
—
GLOBAL.CR1.GPM[1:0]
GLOBAL.CR1.MEIMS
GLOBAL.CR1.G1SROE
—
CONTROL BIT
(IFSEL
42 of 130
≠ 000), there are two general-purpose I/O (GPIO) pins
GLOBAL.GIOACR
and
DS32506/DS32508/DS32512
GLOBAL.GIOBCR
GLOBAL.GIOARR
registers
or