DS32512W Maxim Integrated, DS32512W Datasheet - Page 80

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

9.7 B3ZS/HDB3 Decoder Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: E3 Code Violation Enable (E3CVE). In E3 mode (PORT.CR2:LM[1:0] = 01), this bit specifies whether the
LINE.RBPVCR
in ITU O.161 as consecutive bipolar violations of the same polarity. This bit is ignored in B3ZS mode. See Section
8.3.6.2.
Bit 2: Receive BPV Error Detection Zero Suppression Code Format (REZSF). When REZSF = 0, BPV error
detection detects a B3ZS signature if a zero is followed by a bipolar violation (BPV), and an HDB3 signature if two
zeros are followed by a BPV. When REZSF = 1, BPV error detection detects a B3ZS signature if a zero is followed
by a BPV that has the opposite polarity of the BPV in the previous B3ZS signature, and an HDB3 signature if two
zeros are followed by a BPV that has the opposite polarity of the BPV in the previous HDB3 signature. Note:
Immediately after a reset (RST or DPRST bit high), this bit is ignored. The first B3ZS signature is defined as a zero
followed by a BPV, and the first HDB3 signature is defined as two zeros followed by a BPV. All subsequent
B3ZS/HDB3 signatures are determined by the setting of this bit. Note: The default setting (REZSF = 0) conforms to
ITU O.162. The default setting may falsely ignore actual BPVs that are not codewords. It is recommended that
REZSF be set to one for most applications. This setting is more robust to accurately detect codewords. See
Section 8.3.6.2.
Bit 1: Receive Zero Suppression Decoding Zero Suppression Code Format (RDZSF). When RDZSF = 0, zero
suppression decoding detects a B3ZS signature if a zero is followed by a bipolar violation (BPV), and an HDB3
signature if two zeros are followed by a BPV. When RDZSF = 1, zero suppression decoding detects a B3ZS
signature if a zero is followed by a BPV that has the opposite polarity of the BPV in the previous B3ZS signature,
and an HDB3 signature if two zeros are followed by a BPV that has the opposite polarity of the BPV in the previous
HDB3 signature. Note: Immediately after a reset (RST or DPRST bit high), this bit is ignored. The first B3ZS
signature is defined as a zero followed by a BPV, and the first HDB3 signature is defined as two zeros followed by
a BPV. All subsequent B3ZS/HDB3 signatures are determined by the setting of this bit. Note: The default setting
(RDZSF = 0) may falsely decode actual BPVs that are not codewords. It is recommended that RDZSF be set to
one for most applications. This setting is more robust to accurately detect codewords. See Section 8.3.6.2.
Bit 0: Receive Zero Suppression Decoding Disable (RZSD)
ADDRESS
OFFSET
4Ch
4Ah
4Eh
40h
42h
44h
46h
48h
0 = bipolar violations.
1 = E3 line coding violations
0 = zero suppression (B3ZS or HDB3) decoding is enabled
1 = zero suppression (B3ZS or HDB3) decoding is disabled, and only AMI decoding is performed
15
—
—
register counts bipolar violations or E3 coding violations. Note: E3 line coding violations are defined
0
7
0
LINE.RBPVCR
LINE.REXZCR
LINE.RSRIE
REGISTER
LINE.RSRL
LINE.RCR
LINE.RSR
—
—
14
—
—
0
6
0
LINE.RCR
B3ZS/HDB3 Receive Control Register
n * 80h + 40h
B3ZS/HDB3 Receive Control Register
Unused
B3ZS/HDB3 Receive Status Register
B3ZS/HDB3 Receive Status Register Latched
B3ZS/HDB3 Receive Status Register Interrupt Enable
Unused
B3ZS/HDB3 Receive Bipolar Violation Count Register
B3ZS/HDB3 Receive Excessive Zero Count Register
13
—
—
0
5
0
REGISTER DESCRIPTION
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12
—
—
0
4
0
E3CVE
11
—
0
3
0
REZSF
10
—
0
2
0
DS32506/DS32508/DS32512
RDZSF
—
9
0
1
0
RZSD
—
8
0
0
0