DS32512W Maxim Integrated, DS32512W Datasheet - Page 47

• Manufacturer Part Number: DS32512W
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS32512W

• Part # Aliases: 90-32512-W00

Figure 8-12. Interrupt Signal Flow
8.11 Reset and Power-Down
When only the hardware interface is enabled
pin. The transmitters of all ports can be powered down using the
powered down using the
When a microprocessor interface is enabled
options. The device can be reset at a global level via the GLOBAL.CR1:RST bit or the
level via the PORT.CR1:RST bit. Each port can be powered down via the PORT.CR1:TPD and RPD bits. The
JTAG logic is reset by the
The external
signal. The global reset signal resets all the status and control registers on the chip (except the GLOBAL.CR1:RST
bit), to their default values. It also resets all flip-flops in the global logic (including the CLAD block) and port logic to
their reset values. The GLOBAL.CR1:RST bit stays set after a one is written to it. It is reset to zero when a zero is
written to it or when the external
At the port level, the global reset signal combines with the port reset bit (PORT.CR1:RST) to create a port reset
signal. The port reset signal resets all the status and control registers in the port (except PORT.CR1:RST bit) to
their default values. It also resets all flip-flops in the port logic to their reset values. The port reset bit
(PORT.CR1:RST) stays set after a one is written to it. It is reset to zero when a zero is written to it or when the
global reset signal is active.
The data path reset (RSTDP) resets all of the same registers and flip-flops as the “general” reset (RST), except for
the control registers. This allows the device to be programmed while the data path logic is in reset. It is
recommended that a port be placed in data path reset during configuration changes.
The global data path reset bit (GLOBAL.CR1:RSTDP) is set to one when the global reset signal is active. This bit is
cleared when a zero is written to it while the global reset signal is inactive. The global data path reset resets all of
the data path registers and flip-flops on the chip.
The port data path reset bit (PORT.CR1:RSTDP) is set to one when the port reset signal is active. It is cleared
when a zero is written to it while the port reset signal is inactive. The port data path reset resets all of the port logic
data path registers and flip-flops.
STATUS REGISTER
ENABLE REGISTER
STATUS REGISTER
ENABLE REGISTER
BLOCK LATCHED
AND INTERRUPT
AND INTERRUPT
PORT LATCHED
PORT.SRIE bit
PORT.SRIE bit
RST
PORT.SRL bit
PORT.SRL bit
block SRIE bit
block SRIE bit
block SRL bit
block SRL bit
pin and the global reset bit (GLOBAL.CR1:RST) are combined to create an internal global reset
RPD
JTRST
pin.
RST
pin.
pin is active.
STATUS REGISTER
ENABLE REGISTER
STATUS REGISTER
ENABLE REGISTER
GLOBAL LATCHED
PORT INTERRUPT
AND INTERRUPT
GLOBAL.SRIE bit
GLOBAL.SRIE bit
AND INTERRUPT
GLOBAL.SRL bit
GLOBAL.SRL bit
PORT.ISRIE bit
PORT.ISRIE bit
PORT.ISR bit
PORT.ISR bit
(IFSEL
(IFSEL
≠ 000), the device presents a number of reset and power down
47 of 130
= 000 and
HW
TPD
= 1), the device is can be reset via the
GLOBAL INTERRUPT
STATUS REGISTER
ENABLE REGISTER
pin, while the receivers of all ports can be
GLOBAL.ISRIE bit
GLOBAL.ISRIE bit
AND INTERRUPT
GLOBAL.ISR bit
GLOBAL.ISR bit
DS32506/DS32508/DS32512
RST
pin, and at the port
INT*
RST