CAT9554AWI-G Catalyst (ON Semiconductor), CAT9554AWI-G Datasheet - Page 9

• Manufacturer Part Number: CAT9554AWI-G
• Description: Interface - I/O Expanders 8-Bit Parallel IO
• Manufacturer: Catalyst (ON Semiconductor)

Specifications of CAT9554AWI-G

• Product Category: Interface - I/O Expanders
• Rohs: yes
• Logic Family: CAT9554A
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Interface Type: I2C, SMBus
• Output Current: 50 mA
• Power Dissipation: 1 W
• Factory Pack Quantity: 47

the I/O ports, defined as outputs by the configuration
register. Bit values in this register have no effect on I/O pins
defined as inputs. Reads from the output port register reflect
the value that is in the flip−flop controlling the output, not
the actual I/O pin value.
polarity of the input port register data. If a bit in this register
is set (“1”) the corresponding input port data is inverted. If
a bit in the polarity inversion register is cleared (“0”), the
original input port polarity is retained.
Set the bit in the configuration register to enable the
WRITE TO
DATA OUT FROM PORT
PORT
SDA
REGISTER
SCL
WRITE TO
The output port register sets the outgoing logic levels of
The polarity inversion register allows the user to invert the
The configuration register sets the directions of the ports.
start condition
SDA
SCL
S
1
0
start condition
2
S
1
1
slave address
3
0
0
2
1
4
0 A2
slave address
3
0
5
acknowledge
4
0 A2
from slave
A1
6
Figure 11. Write to Configuration or Polarity Inversion Register
5
acknowledge
A0 0
7
from slave
A1
R/W
6
8
A0 0
7
A
R/W
9
Figure 10. Write to Output Port Register
8
0
A
9
0
acknowledge from slave
0
command byte
0
http://onsemi.com
0
0
acknowledge from slave
command byte
0
0
0
9
0
0
corresponding port pin as an input with a high impedance
output driver. If a bit in this register is cleared, the
corresponding port pin is enabled as an output. At
power−up, the I/Os are configured as inputs with a weak
pull−up resistor to V
the write mode shown in Figure 10 and Figure 11.
timing diagrams shown in Figure 12 and Figure 13. Once a
command byte has been sent, the register which was
addressed will continue to be accessed by reads until a new
command byte will be sent.
0
Data is transmitted to the CAT9554/9554A registers using
The CAT9554/9554A registers are read according to the
0
1
1 1/0
A
A
acknowledge from slave
CC
data to port
DATA 1
.
acknowledge from slave
data to register
DATA 1
t
pv
A P
condition
stop
DATA 1 VALID
A P
condition
stop