CAT9554AWI-G Catalyst (ON Semiconductor), CAT9554AWI-G Datasheet - Page 7

• Manufacturer Part Number: CAT9554AWI-G
• Description: Interface - I/O Expanders 8-Bit Parallel IO
• Manufacturer: Catalyst (ON Semiconductor)

Specifications of CAT9554AWI-G

• Product Category: Interface - I/O Expanders
• Rohs: yes
• Logic Family: CAT9554A
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Interface Type: I2C, SMBus
• Output Current: 50 mA
• Power Dissipation: 1 W
• Factory Pack Quantity: 47

Functional Description
output (GPIO) peripherals provide up to eight I/O ports,
controlled through an I
transmission protocol. This I
device that sends data to the bus to be a transmitter and any
device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the serial
clock and all START and STOP conditions for bus access.
The CAT9554/9554A operate as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls which
mode is activated.
I
The features of the I
2
C Bus Protocol
The CAT9554 and CAT9554A general purpose input/
The CAT9554/9554A support the I
1. Data transfer may be initiated only when the bus is
2. During a data transfer, the data line must remain
not busy.
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition
(Figure 6).
0
Figure 7. CAT9554 Slave Address
1
FIXED
SLAVE ADDRESS
2
0
C bus protocol are defined as follows:
SDA
SCL
2
C compatible serial interface.
0
2
PROGRAMMABLE
C Bus protocol defines any
A2
SELECTABLE
HARDWARE
CONDITION
START
A1
A0
2
Figure 6. START/STOP Condition
C Bus data
R/W
http://onsemi.com
7
START and STOP Conditions
device, and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The CAT9554/9554A monitors the
SDA and SCL lines and will not respond until this condition
is met.
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
address byte is required to enable the CAT9554/9554A for
a read or write operation. The four most significant bits of
the slave address are fixed as binary 0100 for the CAT9554
(Figure 7) and as 0111 for the CAT9554A (Figure 8). The
CAT9554/9554A uses the next three bits as address bits.
device is accessed from maximum eight devices on the same
bus. These bits must compare to their hardwired input pins.
The 8th bit following the 7−bit slave address is the R/W bit
that specifies whether a read or write operation is to be
performed. When this bit is set to “1”, a read operation is
initiated, and when set to “0”, a write operation is selected.
byte, the CAT9554/9554A monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address. The CAT9554/
9554A then performs a read or a write operation depending
on the state of the R/W bit.
The START Condition precedes all commands to the
A LOW to HIGH transition of SDA when SCL is HIGH
After the bus Master sends a START condition, a slave
The address bits A2, A1 and A0 are used to select which
Following the START condition and the slave address
0
Figure 8. CAT9554A Slave Address
1
FIXED
SLAVE ADDRESS
CONDITION
1
STOP
1
PROGRAMMABLE
A2
SELECTABLE
HARDWARE
A1
A0
R/W