CAT9554AWI-G Catalyst (ON Semiconductor), CAT9554AWI-G Datasheet - Page 8

• Manufacturer Part Number: CAT9554AWI-G
• Description: Interface - I/O Expanders 8-Bit Parallel IO
• Manufacturer: Catalyst (ON Semiconductor)

Specifications of CAT9554AWI-G

• Product Category: Interface - I/O Expanders
• Rohs: yes
• Logic Family: CAT9554A
• Operating Supply Voltage: 2.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Interface Type: I2C, SMBus
• Output Current: 50 mA
• Power Dissipation: 1 W
• Factory Pack Quantity: 47

Acknowledge
required to generate an acknowledge. The acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data. The SDA line
remains stable LOW during the HIGH period of the
acknowledge related clock pulse (Figure 6).
after receiving a START condition and its slave address. If
the device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
transmits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this
acknowledge, the CAT9554/9554A will continue to
transmit data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a STOP
condition. The master must then issue a STOP condition to
return the CAT9554/9554A to the standby power mode and
place the device in a known state.
Registers and Bus Transactions
output port register, a polarity inversion register and a
configuration register. Table 7 shows the register address
table. Tables 8 to 11 list Register 0 through Register 3
information.
FROM TRANSMITTER
Table 7. REGISTER COMMAND BYTE
Command
After a successful data transfer, each receiving device is
The CAT9554/9554A responds with an acknowledge
When the CAT9554/9554A begins a READ mode it
The CAT9554/9554A consist of an input port register, an
(hex)
FROM RECEIVER
0x00
0x01
0x02
0x03
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
Read/write byte
Read/write byte
Read/write byte
Read byte
Protocol
START
BUS RELEASE DELAY (TRANSMITTER)
Polarity inversion register
Configuration register
Output port register
Input port register
1
Function
Figure 9. Acknowledge Timing
http://onsemi.com
ACK DELAY
8
8
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine which
register will be written or read.
incoming logic levels of the I/O pins, regardless of whether
the pin is defined as an input or an output by the
configuration register. Writes to the input port register are
ignored.
Table 8. REGISTER 0 – INPUT PORT REGISTER
Table 9. REGISTER 1 – OUTPUT PORT REGISTER
Table 10. REGISTER 2 –
POLARITY INVERSION REGISTER
Table 11. REGISTER 3 – CONFIGURATION REGISTER
The command byte is the first byte to follow the device
The input port register is a read only port. It reflects the
default
default
default
default
bit
bit
bit
bit
9
O
N
C
1
0
1
I
1
ACK SETUP
7
7
7
7
O
N
C
0
1
1
I
1
6
6
6
6
BUS RELEASE DELAY (RECEIVER)
O
N
C
1
0
I
1
1
5
5
5
5
O
N
C
1
0
I
1
1
4
4
4
4
O
N
C
1
0
1
I
1
3
3
3
3
O
N
C
1
0
1
I
1
2
2
2
2
O
N
C
1
0
1
I
1
1
1
1
1
O
N
C
I
1
1
0
1
0
0
0
0