MAX3301EETJ Maxim Integrated, MAX3301EETJ Datasheet - Page 25

• Manufacturer Part Number: MAX3301EETJ
• Description: USB Interface IC
• Manufacturer: Maxim Integrated

Specifications of MAX3301EETJ

• Operating Supply Voltage: 3 V to 4.5 V
• Operating Supply Current: 5 uA

Table 11. Interrupt Latch Register Description (Write to Address 0Ah to Set, Write to
Address 0Bh to Clear)
USB On-the-Go Transceivers and Charge Pumps
Table 12. Interrupt-Enable Low Register (Write to Address 0Ch to Set, Write to Address
0Dh to Clear)
BIT NUMBER
BIT NUMBER
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
cr_int_sess_end
______________________________________________________________________________________
bdis_acon
SYMBOL
vbus_vld
sess_vld
id_float
cr_int_sess_end
id_gnd
dm_hi
dp_hi
bdis_acon
SYMBOL
vbus_vld
sess_vld
id_gnd
id_float
dm_hi
dp_hi
vb us_vl d asser ts i f a tr ansi ti on occur s on thi s cond i ti on and the ap p r op r i ate
i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. S ee Tab l es 10, 12, and 13.
sess_vl d asser ts i f a tr ansi ti on occur s on thi s cond i ti on and the ap p r op r i ate
i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. S ee Tab l es 10, 12, and 13.
d p _hi asser ts i f a tr ansi ti on occur s on thi s cond i ti on and the ap p r op r i ate i nter r up t-
hi g h or i nter r up t- l ow enab l e b i t i s set. S ee Tab l es 10, 12, and 13.
i d _g nd asser ts i f a tr ansi ti on occur s on thi s cond i ti on and the ap p r op r i ate i nter r up t-
hi g h or i nter r up t- l ow enab l e b i t i s set. S ee Tab l es 10, 12, and 13.
d m _hi asser ts i f a tr ansi ti on occur s on thi s cond i ti on and the ap p r op r i ate i nter r up t-
hi g h or i nter r up t- l ow enab l e b i t i s set. S ee Tab l es 10, 12, and 13.
i d _fl oat asser ts i f a tr ansi ti on occur s on thi s cond i ti on and the ap p r op r i ate i nter r up t-
hi g h or i nter r up t- l ow enab l e b i t i s set. S ee Tab l es 10, 12, and 13.
b d i s_acon asser ts i f a tr ansi ti on occur s on thi s cond i ti on and the ap p r op r i ate
i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. S ee Tab l es 10, 12, and 13.
cr _i nt_sess_end asser ts i f a tr ansi ti on occur s on thi s cond i ti on and the ap p r op r i ate
i nter r up t- hi g h or i nter r up t- l ow enab l e b i t i s set. S ee Tab l es 10, 12, and 13.
S et to 0 to d i sab l e the vb us_vld i nter rup t for a hig h- to- l ow transiti on. S et to 1 to
enab l e the vb us_vld i nter rup t for a hig h- to- l ow transiti on. S ee Tab l es 10 and 11.
S et to 0 to d i sab l e the sess_vld i nter rup t for a hig h- to- l ow transiti on. S et to 1 to
enab l e the sess_vld i nter rup t for a hig h- to- l ow transiti on. S ee Tab l es 10 and 11.
S et to 0 to d i sab l e the d p _hi interr up t for a hi g h-to- low tr ansi ti on. Set to 1 to
enab l e the d p _hi interr up t for a hi g h-to- low tr ansi ti on. See Tab l es 10 and 11.
S et to 0 to d i sab l e the i d _g nd i nter r upt for a hi g h- to-l ow tr ansi tion. S et to 1 to
enab l e the i d _g nd i nter r upt for a hi g h- to-l ow tr ansi tion. S ee Tab les 10 and 11.
S et to 0 to d i sab l e the d m _hi interr up t for a hi g h-to- low tr ansi ti on. Set to 1 to
enab l e the d m _hi interr up t for a hi g h-to- low tr ansi ti on. See Tab l es 10 and 11.
S et to 0 to d i sab l e the i d _fl oat i nter rup t for a hig h- to- l ow transiti on. S et to 1 to
enab l e the i d _fl oat i nter rup t for a hig h- to- l ow transiti on. S ee Tab l es 10 and 11.
S et to 0 to d i sab l e the b d is_acon interr up t for a hi g h-to- low tr ansi ti on. Set to 1 to
enab l e the b d is_acon interr up t for a hi g h-to- low tr ansi ti on. See Tab l es 10 and 11.
S et to 0 to d i sab l e the cr _i nt_sess_end i nter r up t for a hi g h- to- l ow tr ansi ti on.
S et to 1 to enab l e the cr _i nt_sess_end i nter r up t for a hi g h- to- l ow tr ansi ti on.
S ee Tab l es 10 and 11.
CONTENTS
CONTENTS
POWER-UP
POWER-UP
VALUE AT
VALUE AT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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