MAX3301EETJ Maxim Integrated, MAX3301EETJ Datasheet - Page 16

• Manufacturer Part Number: MAX3301EETJ
• Description: USB Interface IC
• Manufacturer: Maxim Integrated

Specifications of MAX3301EETJ

• Operating Supply Voltage: 3 V to 4.5 V
• Operating Supply Current: 5 uA

A register file controls the various internal switches and
operating modes of the MAX3301E/MAX3302E through
a simple 2-wire interface operating at clock rates up to
400kHz. This interface supports data bursting, where
multiple data phases can follow a single address phase.
Set uart_en (bit 6 in control register 1) to 1 to place the
MAX3301E/MAX3302E in UART mode. D+ transfers
data to DAT_VP and SE0_VM transfers data to D- in
UART mode.
Set gp_en (bit 7 in special-function register 1) and
dat_se0 (bit 2 in control register 1) to 1, set uart_en (bit 6
in control register 1) to 0, and drive OE/INT low to place
the MAX3301E/MAX3302E in general-purpose buffer
mode. Control the direction of data transfer with dmi-
nus_dir and dplus_dir (bits 3 and 4 of special-function
register 1, see Tables 2 and 14).
The MAX3301E/MAX3302E operate as a slave device
that sends and receives control and status signals
through an I
face uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master (typically a microcon-
troller) initiates all data transfers to and from the
MAX3301E/MAX3302E and generates the SCL clock
that synchronizes the data transfer (Figure 13).
The MAX3301E/MAX3302E SDA line operates as both an
input and as an open-drain output. SDA requires a
USB On-the-Go Transceivers and Charge Pumps
16
Figure 13. 2-Wire Serial-Interface Timing Details
t
HD: STA
SDA
SCL
______________________________________________________________________________________
2-Wire I
CONDITION
START
2
C-compatible 2-wire interface. The inter-
2
C-Compatible Serial Interface
t
LOW
General-Purpose Buffer Mode
t
R
t
HIGH
t
SU: DAT
t
F
Serial Addressing
t
HD: DAT
UART Mode
t
SU: STA
REPEATED START
CONDITION
pullup resistor, typically 4.7kΩ. The MAX3301E/
MAX3302E SCL line only operates as an input. SCL
requires a pullup resistor if there are multiple masters on
the 2-wire interface, or if the master in a single-master
system has an open-drain SCL output.
Each transmission consists of a start condition (see
Figure 14) sent by a master device, the MAX3301E/
MAX3302E 7-bit slave address (determined by the state
of ADD), plus an R/W bit (see Figure 15), a register
address byte, one or more data bytes, and a stop condi-
tion (see Figure 14).
Table 2. Setting the Direction of Data
Transfer in General-Purpose Buffer Mode
dplus_dir
t
HD: STA
0
0
1
1
dminus_ dir
t
SU: STO
0
1
0
1
CONDITION
STOP
DIRECTION OF DATA
t
BUF
CONDITION
DAT_VP → D+
DAT_VP → D+
DAT_VP ← D+
DAT_VP ← D+
SE0_VM → D-
SE0_VM ← D-
SE0_VM → D-
SE0_VM ← D-
TRANSFER
START