MAX9271GTJ+T Maxim Integrated, MAX9271GTJ+T Datasheet - Page 37

• Manufacturer Part Number: MAX9271GTJ+T
• Description: Serializers & Deserializers - Serdes 1.5Gbps 16Bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9271GTJ+T

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 16
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-32
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To run
the PRBS test, set PRBSEN = 1 (0x04, D5) in the deserial-
izer and then in the serializer. To exit the PRBS test, set
PRBSEN = 0 (0x04, D5) in the serializer.
The serializer contains an error generator that enables
repeatable testing of the error-detection/correction fea-
tures of the GMSL link. Register 0x11 stores the configu-
ration bits for the error generator. A FC sets the error-
generation rate, type of errors, and the total number of
errors. The error generator is off by default.
Usually systems have one FC to run the control channel,
located on the serializer side for video-display appli-
cations or on the deserializer side for image-sensing
applications. However, a FC can reside on each side
simultaneously and trade off running the control channel.
In this case, each FC can communicate with the serializer
and deserializer and any peripheral devices.
Contention occurs if both FC s attempt to use the control
channel at the same time. It is up to the user to prevent
this contention by implementing a higher-level protocol.
In addition, the control channel does not provide arbitra-
tion between I
acknowledge frame is not generated when communica-
tion fails due to contention. If communication across the
serial link is not required, the FC s can disable the for-
ward and reverse control channel using the FWDCCEN
and REVCCEN bits (0x04, D[1:0]) in the serializer/dese-
rializer. Communication across the serial link is stopped
and contention between FC s cannot occur.
As an example of dual FC use in an image-sensing appli-
cation, the serializer can be in sleep mode, waiting for
wake-up by the FC on the deserializer side. After wake-
up, the serializer-side FC assumes master control of the
serializer’s registers.
In some applications, the clock input (PCLKIN) includes
noise, which reduces link reliability. The clock input has a
programmable narrowband jitter-filter PLL that attenuates
frequencies higher than 100kHz (typ). Enable the jitter
filter by setting ENJITFILT = 1 (0x05, D6).
Maxim Integrated
2
C masters on both sides of the link. An
Applications Information
Jitter-Filtering PLL
16-Bit GMSL Serializer with Coax or
Error Generator
Dual µC Control
PRBS Test
The serializer can operate with a spread PCLKIN
signal. When using a spread PCLKIN signal, disable the
jitter filter by setting ENJITFILT = 0 (0x05, D6). Do not
exceed the spread limitations listed in
modulation less than 40kHz. In addition, turn off spread
spectrum in the serializer/deserializer. The serializer/
deserializer track the spread on PCLKIN.
It is recommended that the serial link be enabled after
the video clock (f
(f
stop the video clock for 5Fs, apply the clock at the new
frequency, then restart the serial link or toggle SEREN.
On-the-fly changes in clock frequency are possible if
the new frequency is immediately stable and without
glitches. The reverse control channel remains unavail-
able for 350Fs after serial link start or stop. When using
the UART interface, limit on-the-fly changes in f
factors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps, then at 100kbps for reduction
ratios of 3 and 3.333, respectively.
The GPI and GPO provide a simple solution for camera
applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input and connect the GPO
output to the camera frame sync input. GPI/GPO have
a typical delay of 275Fs. Skew between multiple GPI/
GPO channels is 115Fs (max). If a lower skew signal is
required, connect the camera’s frame sync input to one
of the serializer’s GPIOs and use an I
command to change the GPIO output state. This has a
maximum skew of 1.5Fs, independent from the used I
bit rate.
The serializer and deserializer have programmable device
addresses. This allows multiple GMSL devices, along with
I
The serializer device address is in register 0x00 of each
device, while the deserializer device address is in register
0x01 of each device. To change a device address, first
2
UART
C peripherals, to coexist on the same control channel.
/f
I2C
) are stable. When changing clock frequency,
Changing the Clock Frequency
PCLKIN
Software Programming of the
STP Cable Drive
) and the control-channel clock
PCLKIN Spread Tracking
Providing a Frame Sync
(Camera Applications)
Device Addresses
MAX9271
2
C broadcast write
Table 7
and keep
UART
2
37
to
C