MAX9271GTJ+T Maxim Integrated, MAX9271GTJ+T Datasheet - Page 27

• Manufacturer Part Number: MAX9271GTJ+T
• Description: Serializers & Deserializers - Serdes 1.5Gbps 16Bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9271GTJ+T

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 16
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-32
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Figure 23. Format Conversion Between GMSL UART and I
In I
face sends and receives data through an I
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirec-
tional communication between master and slave(s). A
FC master initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer. When an I
local-side device’s control-channel port, the remote-side
device’s control-channel port becomes an I
that interfaces with remote-side I
master must accept clock stretching, which is imposed
by the serializer (holding SCL low). The SDA and SCL
lines operate as both an input and an open-drain output.
Pullup resistors are required on SDA and SCL. Each
transmission consists of a START condition
sent by a master, followed by the device’s 7-bit slave
address plus a R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from
high to low while SCL is high (see
Maxim Integrated
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
2
C-to-I
FC
FC
SYNC FRAME
SYNC FRAME
2
UART-TO-I
UART-TO-I
C mode the serializer’s control-channel inter-
11
11
2
2
C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
C CONVERSION OF READ PACKET (I2CMETHOD = 1)
SERIALIZER/DESERIALIZER
SERIALIZER/DESERIALIZER
DEVICE ID + RD
DEVICE ID + WR
START and STOP Conditions
11
11
2
PERIPHERAL
PERIPHERAL
C transaction starts on the
: MASTER TO SLAVE
2
C perhipherals. The I
S
1
REGISTER ADDRESS
REGISTER ADDRESS
16-Bit GMSL Serializer with Coax or
Figure
DEV ID
7
11
11
I
2
2
C Interface
24). When the
W A
C-compatible
1
1
2
(Figure
: SLAVE TO MASTER
C master
NUMBER OF BYTES
NUMBER OF BYTES
2
C with Register Address (I2CMETHOD = 1)
11
2
11
6)
C
1
S
S: START
DEV ID
master has finished communicating with the slave, it
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission.
One data bit is transferred during each clock pulse
(Figure
SCL is high.
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data
Thus, each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the
forward control channel is not active (not locked). To pre-
vent acknowledge generation when the forward control
channel is not active, set the I2CLOCACK.
7
DATA 0
1 1
R A
11
25). The data on SDA must remain stable while
P: STOP
ACK FRAME
DATA 0
11
8
A: ACKNOWLEDGE
DATA 0
8
1
A
STP Cable Drive
DATA N
1
A
11
DATA 0
11
DATA N
8
DATA N
MAX9271
A P
1 1
8
ACK FRAME
11
1 1
A P
Acknowledge
DATA N
Bit Transfer
11
(Figure
26).
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