MAX9271GTJ/V+ Maxim Integrated, MAX9271GTJ/V+ Datasheet - Page 18

• Manufacturer Part Number: MAX9271GTJ/V+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 16-bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9271GTJ/V+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 16
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-32
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Figure 12. Power-Up Delay
The MAX9271 serializer, when paired with the MAX9272
deserializer, provides the full set of operating features,
but offers basic functionality when paired with any GMSL
deserializer.
The serializer has a maximum serial-bit rate of 1.5Gbps
for 15m or more of cable and operates up to a maximum
input clock of 50MHz in 16-bit, single-input mode, or
75MHz/100MHz in 15-bit/11-bit, double-input mode,
respectively. Pre/deemphasis, along with the GMSL
deserializer channel equalizer, extends the link length
and enhances link reliability.
The control channel enables a FC to program serial-
izer and deserializer registers and program registers
on peripherals. The FC can be located at either end of
the link or at both ends. Two modes of control-channel
operation are available with associated protocols and
data formats. Base mode uses either I
protocol, while bypass mode uses a user-defined UART
protocol.
Spread spectrum is available to reduce EMI on the serial
output. The serial output complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
Maxim Integrated
PWDN
CHANNEL DISABLED
PCLKIN
REVERSE CONTROL
POWERED DOWN
Detailed Description
16-Bit GMSL Serializer with Coax or
2
V
IH1
C or GMSL UART
SERIAL LINK INACTIVE
CHANNEL ENABLED
REVERSE CONTROL
POWERED UP,
t
PU
Registers set the operating conditions of the serializer
and are programmed using the control channel in base
mode. The serializer holds its device address and the
device address of the deserializer it is driving. Similarly,
the driven deserializer holds its device address and the
address of the serializer by which it is driven. Whenever a
device address is changed, the new address should be
written to both devices. The default device address of the
MAX9271 serializer (or any GMSL serializer) is 0x80 and
the default device address of any GMSL deserializer is
0x90
hold the device addresses.
The parallel input functioning and width depends on
settings of the double-/single-input mode (DBL), HS/VS
encoding (HVEN), error correction (EDC), and bus width
(BWS) pins. DINA is the input latched by the pixel clock
in single-input mode, or the inputs latched on the first
pixel clock in double-input mode. DINB are the inputs
latched on the second pixel clock in double-input mode.
Table 2
CHANNEL DISABLED
REVERSE CONTROL
(Table
350µs
lists the bit map for the control pin settings.
POWERED UP, SERIAL LINK ACTIVE
1). Registers 0x00 and 0x01 in both devices
STP Cable Drive
CHANNEL ENABLED
REVERSE CONTROL
Register Mapping
MAX9271
Input Bit Map
18