MAX9271GTJ/V+ Maxim Integrated, MAX9271GTJ/V+ Datasheet - Page 12

• Manufacturer Part Number: MAX9271GTJ/V+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 16-bit Coax/STP serializer
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX9271GTJ/V+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CMOS/LVCMOS
• Output Type: CML
• Number Of Inputs: 16
• Number Of Outputs: 1
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-32
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Maxim Integrated
PIN
13
14
15
16
17
18
19
20
21
23
24
25
29
—
RX/SDA/EDC
TX/SCL/DBL
GPIO1/BWS
MS/HVEN
PCLKIN
LCCEN
CONF0
CONF1
NAME
PWDN
DVDD
OUT+
OUT-
GPO
EP
16-Bit GMSL Serializer with Coax or
General-Purpose Output. GPO follows the GMSL deserializer GPI (or INT) input.
GPO = low upon power-up and when PWDN = low.
GPIO/Bus Width Select Input. Function is determined by the state of LCCEN (Table 13).
Mode Select/HS and VS Encoding Enable with Internal Pulldown to EP. Function is
determined by the state of LCCEN (Table 13).
Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter
power-down mode to reduce power consumption.
Local Control-Channel Enable Input with Internal Pulldown to EP. LCCEN = high enables
the control-channel interface pins. LCCEN = low disables the control-channel interface
pins and selects an alternate function on the indicated pins (Table 13).
Configuration 0. Three-level configuration input (Table 9).
Configuration 1. Three-level configuration input (Table 9).
Inverting Coax/Twisted-Pair Serial Output
Noninverting Coax/Twisted-Pair Serial Output
Receive/Serial Data/Error-Detection/Correction. Function is determined by the state of
LCCEN (Table 13).
Transmit/Serial Clock/Double Mode. Function is determined by the state of LCCEN
(Table 13).
Parallel Clock Input with Internal Pulldown to EP. Latches parallel data inputs and
provides the PLL reference clock.
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller value capacitor closest to DVDD.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB
ground plane through an array of vias for proper thermal and electrical performance.
GPIO1 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kI
pullup to IOVDD.
BWS (LCCEN = low): Input with internal pulldown to EP. Set BWS = low for 22-bit input
latch. Set BWS = high for 30-bit input latch.
MS (LCCEN = high): Set MS = low to select base mode. Set MS = high to select the
bypass mode.
HVEN (LCCEN = low): Set HVEN = high to enable HS/VS encoding on DIN14/HS and
DIN15/VS. Set HVEN = low to use DIN14/HS and DIN15/VS as parallel data inputs.
RX/SDA (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART
mode, RX/SDA is the Rx input of the serializer’s UART. In I
SDA input/output of the serializer’s I
and requires a pullup resistor.
EDC (LCCEN = low): Input with internal pulldown to EP. Set EDC = high to enable
error-detection correction. Set EDC = low to disable error-detection correction.
TX/SCL (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART
mode, TX/SCL is the Tx output of the serializer’s UART. In the I
the SCL input/output of the serializer’s I
driver and requires a pullup resistor.
DBL (LCCEN = low): Input with internal pulldown to EP. Set DBL = high to use double-
input mode. Set DBL = low to use single-input mode.
2
C master/slave. RX/SDA has an open-drain driver
FUNCTION
2
Pin Description (continued)
C master/slave. TX/SCL has an open-drain
STP Cable Drive
2
C mode, RX/SDA is the
2
C mode, TX/SCL is
MAX9271
12