MAX9272GTM/V+ Maxim Integrated, MAX9272GTM/V+ Datasheet - Page 28

• Manufacturer Part Number: MAX9272GTM/V+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 28-bit Coax/STP deserializr
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9272GTM/V+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CML
• Output Type: CMOS/LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 28
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
One data bit is transferred during each clock pulse
(Figure
SCL is high.
Figure 22. START and STOP Conditions
Figure 23. Bit Transfer
Figure 24. Acknowledge
Maxim Integrated
28-Bit GMSL Deserializer for Coax or STP Cable
23). The data on SDA must remain stable while
SDA
SCL
TRANSMITTER
RECEIVER
SDA
SCL
SCL
SDA
SDA
CONDITION
BY
BY
START
S
CONDITION
START
(Figure
S
START and STOP Conditions
22). When the master has
DATA LINE STABLE;
DATA VALID
1
Bit Transfer
CHANGE OF DATA
ALLOWED
2
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data
24). Thus, each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the for-
ward control channel is not active (not locked). To prevent
acknowledge generation when the forward control chan-
nel is not active, set the I2CLOCACK bit low.
8
CLOCK PULSE FOR
ACKNOWLEDGE
MAX9272
9
CONDITION
STOP
P
Acknowledge
(Figure
28