MAX9272GTM/V+ Maxim Integrated, MAX9272GTM/V+ Datasheet - Page 21

• Manufacturer Part Number: MAX9272GTM/V+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 28-bit Coax/STP deserializr
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9272GTM/V+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CML
• Output Type: CMOS/LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 28
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Table 1. Power-Up Default Register Map (see
Maxim Integrated
REGISTER
ADDRESS
(hex)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
28-Bit GMSL Deserializer for Coax or STP Cable
0x02 or 0x22
POWER-UP
DEFAULT
0x90 or
(hex)
0xXX
0x80
0x92
0x1F
0x00
0x07
0x24
SERID = 1000000, serializer device address
RESERVED = 0
DESID = 1001000 (CX/TP = high or low), DESID = 1001001 (CX/TP = midlevel), deserializer
device address is determined by the state of the CX/TP input at power-up
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
SS = 00, spread spectrum disabled
RESERVED = 01
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
AUTOFM = 00, calibrate spread-modulation rate only once after locking
RESERVED = 0
SDIV = 00000, autocalibrate sawtooth divider
LOCKED = 0, LOCK output is low (read only)
OUTENB = 0, output enabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0, sleep mode deactivated (see the Link Startup Procedure section)
INTTYPE = 01, base mode uses UART
REVCCEN = 1, reverse control channel active (sending)
FWDCCEN = 1, forward control channel active (receiving)
I2CMETHOD = 0, I
DCS = 0, normal parallel output driver current
HVTRMODE = 1, full periodic HS/VS tracking
ENEQ = 0, equalizer disabled
EQTUNE = 1001, 10.7dB equalization
RESERVED = 00X00010
DBL = 0 or 1, single-/double-input mode setting determined by the state of LCCEN and
GPIO0/DBL at startup
DRS = 0, high data-rate mode
BWS = 0 or 1, bit width setting determined by the state of LCCEN and GPIO1/BWS at startup
ES = 0 or 1, edge-select input setting determined by the state of LCCEN and TX/SCL/ES at startup
HVTRACK = 0 or 1, HS/VS tracking setting determined by the state of LCCEN and MS/HVEN at
startup
HVEN = 0 or 1, HS/VS tracking encoding setting determined by the state of LCCEN and MS/HVEN
at startup
EDC = 00 or 10, error-detection/correction setting determined by the state of LCCEN and
RX/SDA/EDC at startup
2
C master sends the register address
POWER-UP DEFAULT SETTINGS
Table
(MSB FIRST)
16)
MAX9272
21