MAX9272GTM/V+ Maxim Integrated, MAX9272GTM/V+ Datasheet - Page 14

• Manufacturer Part Number: MAX9272GTM/V+
• Description: Serializers & Deserializers - Serdes 1.5Gbps 28-bit Coax/STP deserializr
• Manufacturer: Maxim Integrated
• Type: Deserializerr

Specifications of MAX9272GTM/V+

• Rohs: yes
• Data Rate: 1.5 Gbit/s
• Input Type: CML
• Output Type: CMOS/LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 28
• Operating Supply Voltage: 1.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: TQFN-48
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

Maxim Integrated
21–40,
20, 41
42–45
PIN
19
46
47
—
28-Bit GMSL Deserializer for Coax or STP Cable
DOUT24/HS0
PCLKOUT
DOUT23–
MS/HVEN
DOUT0
IOVDD
NAME
EP
DOUT24/HS0
DOUT25 / VS0
DOUT26/HS1
DOUT27/ VS1
DOUT [23:0]
GPIO1/BWS
GPIO0/DBL
PCLKOUT
GPI
Parallel Data/Horizontal Sync 0 Output. Defaults to parallel data input on power-up.
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1FF and 0.001FF
capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD.
Parallel Data Outputs
Parallel Clock Output. Latches parallel data into the input of another device.
Mode Select/HS and VS Encoding Enable with Internal Pulldown to EP. Function is determined by the
state of LCCEN (Table 13).
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB ground
plane through an array of vias for proper thermal and electrical performance.
Parallel data output when VS/HS encoding is disabled.
Decoded horizontal sync for lower half of single-output when VS/HS encoding is enabled (Table 2).
MS (LCCEN = high). Set MS = low to select base mode. Set MS = high to select the bypass mode.
HVEN (LCCEN = low): Set HVEN = high to enable HS/VS encoding on DOUT_/HS_ and DOUT_/VS_.
Set HVEN = low to use DOUT_/HS_ and DOUT_/VS_ as parallel data outputs.
VS / HS
GPIO
1x[27:0]
2x[10:0]
2x[14:0]
FIFO
OR
OR
SSPLL
FCC
SCRAMBLE/
HAMMING/
DECODE
8b/10b
CRC/
CLKDIV
TX/SCL/ES
FUNCTION
UART/I
CDRPLL
PARALLEL
SERIAL
TO
2
RX/SDA/EDC
C
CONTROL
CHANNEL
REVERSE
Pin Description (continued)
MAX9272
T
x
CML Rx
AND EQ
Functional Diagram
MAX9272
IN+
IN-
14