MAX13003EEUE+ Maxim Integrated Products, MAX13003EEUE+ Datasheet - Page 18

• Manufacturer Part Number: MAX13003EEUE+
• Description: IC LEVEL TRANS 6CH 16-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX13003EEUE+

• Logic Function: Translator, Bidirectional
• Number Of Bits: 6
• Input Type: CMOS
• Output Type: CMOS
• Data Rate: 20Mbps
• Number Of Channels: 1
• Number Of Outputs/channel: 6
• Differential - Input:output: No/No
• Propagation Delay (max): 15ns
• Voltage - Supply: 1.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Supply Voltage: 1.5 V ~ 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The IEC 61000-4-2 standard (Figure 12) specifies ESD
tolerance for electronic systems. The IEC61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330Ω resistor. The
MAX13000E–MAX13005E’s I/O on the V
rated for IEC 61000-4-2 standard, (8kV Contact
Discharge and ±10kV Air-Gap Discharge).
The IEC 61000-4-2 model discharges higher peak cur-
rent and more energy than the HBM due to the lower
series resistance and larger capacitor.
To reduce ripple and the chance of transmitting incor-
rect data, bypass V
capacitor. To ensure full ±15kV ESD protection, bypass
V
tors as close to the power-supply inputs as possible.
Ultra-Low-Voltage Level Translators
Figure 10. Human Body ESD Test Model
Figure 11. Human Body Current Waveform
18
CC
AMPERES
VOLTAGE
SOURCE
IEC 61000-4-2 Standard ESD Protection
______________________________________________________________________________________
to ground with a 1µF capacitor. Place all capaci-
HIGH-
DC
I
P
36.8%
100%
CHARGE-CURRENT-
90%
10%
LIMIT RESISTOR
0
0
R
Applications Information
C
t
100pF
RL
1MΩ
C
S
L
and V
Power-Supply Decoupling
CURRENT WAVEFORM
RESISTANCE
DISCHARGE
R
TIME
STORAGE
CAPACITOR
D
1500Ω
CC
t
DL
I
r
to ground with a 0.1µF
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
CC
DEVICE
UNDER
side are
TEST
For general UCSP package information and PC layout
considerations, please refer to Maxim application note:
Wafer-Level Chip-Scale Package.
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
Figure 12. IEC 61000-4-2 Contact Discharge Test Model
VOLTAGE
SOURCE
HIGH-
DC
CHARGE-CURRENT-
LIMIT RESISTOR
50Ω TO 100Ω
R
UCSP Package Considerations
C
150pF
C s
STORAGE
CAPACITOR
RESISTANCE
DISCHARGE
330Ω
R
D
UCSP Reliability
DEVICE
UNDER
TEST