MAX11060GUU+T Maxim Integrated, MAX11060GUU+T Datasheet - Page 12

• Manufacturer Part Number: MAX11060GUU+T
• Description: Analog to Digital Converters - ADC 24/16Bit 4Ch Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11060GUU+T

• Rohs: yes
• Number Of Channels: 4
• Architecture: SAR
• Input Type: Single-Ended/Pseudo-Differential
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 3.6 V, 3 V to 3.6 V
• Maximum Power Dissipation: 1096 mW
• Number Of Converters: 4

The MAX11040K/MAX11060 are 24-/16-bit, simultane-
ous-sampling, 4-channel, sigma-delta ADCs including
support for synchronized sampling and daisy chaining
of the serial interface across multiple (up to eight)
devices. The serial interface of the set of synchronized
devices behaves as one device. Each channel includes
a differential analog input, a sigma-delta modulator, a
digital decimation filter, an independent programmable
sampling delay, and a buffered reference signal from
the internal or an external reference. The device con-
tains an internal crystal oscillator. The output data rate,
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
MAX11040K/MAX11060
12
AIN0+
AIN1+
AIN2+
AIN3+
AIN0-
AIN1-
AIN2-
AIN3-
1µF
1µF
1µF
1µF
1µF
AIN0+
AIN0-
REF0
AIN1+
AIN1-
REF1
AIN2+
AIN2-
REF2
AIN3+
AIN3-
REF3
REFIO
0.01µF
1µF
AGND
Typical Operating Circuit
AVDD
3.3V
MAX11040K
MAX11060
Detailed Description
DVDD
3.3V
DGND
CASCOUT
DRDYOUT
0.01µF
OVRFLW
CLKOUT
CASCIN
DRDYIN
1µF
FAULT
XOUT
DOUT
SYNC
SCLK
DIN
XIN
CS
24.576MHz
MICROCONTROLLER
20pF
20pF
OR DSP
the effective sample rate of the ADC, is software pro-
grammable.
The devices operate from a single 3.0V to 3.6V analog
supply and a 2.7V to V
serial interface is SPI/QSPI/MICROWIRE and DSP com-
patible.
Each channel of the devices performs analog-to-
digital conversion on its input using a dedicated
switched-capacitor sigma-delta modulator. The modula-
tor converts the input signal into low-resolution digital data
for which the average value represents the digitized sig-
nal information at 3.072Msps for a 24.576MHz XIN clock.
This data stream is then presented to the digital filter for
processing to remove the high-frequency noise that cre-
ates a high-resolution 24-/16-bit output data stream.
The input sampling network of the analog input consists
of a pair of 4pF capacitors (C
plates of which are connected to AIN_+ and AIN_- dur-
ing the track phase and then shorted together during
the hold phase (see Figure 1). The internal switches
have a total series resistance of 400Ω. Given a
24.576MHz XIN clock, the switching frequency is
3.072MHz. The sampling phase lasts for 120ns.
Figure 1. Simplified Track/Hold Stage
AIN_+
AIN_-
HOLD
TRACK
TRACK
AVDD
MAX11040K
MAX11060
C
C
SAMPLE+
SAMPLE-
digital supply. The 4-wire
R
ON
SAMPLE
AVDD/2
ADC Modulator
TO ADC
R
), the bottom
ON
Maxim Integrated