MAX11127ATI+ Maxim Integrated, MAX11127ATI+ Datasheet - Page 30

• Manufacturer Part Number: MAX11127ATI+
• Description: Analog to Digital Converters - ADC 10Bit 16Ch 1Msps Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11127ATI+

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 1 MSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 61.7 dB
• Interface Type: 3-Wire, QSPI, SPI
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-28
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 1 V

Table 7. RANGE Register (RANGE Settings Only Applies to Bipolar Fully Differential
Analog Input Configurations)
The ADC Scan Control register
ADC mode of operation. The Unipolar and Bipolar regis-
ters in
and whether input configuration is single-ended or fully
differential.
Table 9
AIN0 and AIN1. The truth table is consistent for any other
valid input pairs (AINn/AINn+1).
cable input signal format with respect to analog input
configurations.
CHSEL[3:0]
STANDARD_EXT,
UPPER_INT modes of operation. CHSCAN[15:0] is used
for CUSTOM_EXT and CUSTOM_INT modes of operation.
Maxim Integrated
RANGE_SETUP
RANGE10/11
RANGE12/13
RANGE14/15
BIT NAME
RANGE0/1
RANGE2/3
RANGE4/5
RANGE6/7
RANGE8/9
Table 10
details the conversion output for analog inputs,
—
is
and
of Unipolar and Bipolar Modes
used
ADC OUTPUT as a Function
Table 11
STANDARD_INT,
15:11
BIT
2:0
10
9
8
7
6
5
4
3
for
1Msps, Low-Power, Serial 12-/10-/8-Bit,
determine output coding
(Table
Table 8
MANUAL,
DEFAULT
STATE
N/A
000
3) determines the
0
0
0
0
0
0
0
0
shows the appli-
UPPER_EXT,
REPEAT,
Set to 10011 to select the RANGE register
Set to 0 for AIN0/1: +V
Set to 1 for AIN0/1: +V
Set to 0 for AIN2/3: +V
Set to 1 for AIN2/3: +V
Set to 0 for AIN4/5: +V
Set to 1 for AIN4/5: +V
Set to 0 for AIN6/7: +V
Set to 1 for AIN6/7: +V
Set to 0 for AIN8/9: +V
Set to 1 for AIN8/9: +V
Set to 0 for AIN10/11: +V
Set to 1 for AIN10/11: +V
Set to 0 for AIN12/13: +V
Set to 1 for AIN12/13: +V
Set to 0 for AIN14/15: +V
Set to 1 for AIN14/15: +V
Unused
The SampleSet register stores the unique channel
sequence length. The sequence pattern is comprised of
up to 256 unique single-ended and/or differential conver-
sions with any order or pattern.
Patterns are assembled in 4-bit channel identifier nib-
bles as described in
SampleSet timing diagram. Note that two CS frames are
required to configure the SampleSet functionality. The
first frame indicates the sequence length. The second
frame is used to encode the channel sequence pattern.
After the SampleSet register has been coded
by the next falling edge of CS, the new SampleSet pattern
is activated
SEQ_LENGTH, the remaining channels default to AIN0. If
the select pattern length is greater than SEQ_LENGTH,
the additional data is ignored as the ADC waits for the ris-
ing edge of CS. If CS is asserted in the middle of a nibble,
the full nibble defaults to AIN0.
MAX11120–MAX11128
4-/8-/16-Channel ADCs
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF+
/2
/2
/2
/2
/2
(Figure
/2
/2
/2
FUNCTION
SampleSet Mode of Operation
10). If the pattern length is less than
Table
4.
Figure 10
presents the
(Table
14),
30