MAX11127ATI+ Maxim Integrated, MAX11127ATI+ Datasheet - Page 16

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MAX11127ATI+

Manufacturer Part Number
MAX11127ATI+
Description
Analog to Digital Converters - ADC 10Bit 16Ch 1Msps Precision ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX11127ATI+

Rohs
yes
Number Of Channels
16/8
Architecture
SAR
Conversion Rate
1 MSPs
Resolution
10 bit
Input Type
Single-Ended/Pseudo-Differential
Snr
61.7 dB
Interface Type
3-Wire, QSPI, SPI
Operating Supply Voltage
2.35 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
TQFN-28
Maximum Power Dissipation
2758 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
1 V
Maxim Integrated
(4 CHANNEL)
26, 27, 28, 1
MAX11120
MAX11121
MAX11122
14, 16
17, 18
2–11
12
13
15
19
20
21
22
23
24
25
26, 27, 28, 1–5
(8 CHANNEL)
MAX11123
MAX11124
MAX11125
14, 16
17, 18
6–11
12
13
15
19
20
21
22
23
24
25
1Msps, Low-Power, Serial 12-/10-/8-Bit,
(16 CHANNEL)
MAX11126
MAX11127
MAX11128
26, 27, 28,
14, 16
17, 18
1–11
12
13
15
19
20
21
22
23
24
25
AIN0–AIN13
AIN0–AIN7
AIN0–AIN3
CNVST/
CNVST
NAME
DGND
OVDD
AIN14
AIN15
DOUT
REF-/
REF+
SCLK
GND
GND
REF-
EOC
V
DIN
CS
EP
DD
Analog Inputs
Analog Inputs
Analog Inputs
Ground
Active-Low Conversion Start Input/Analog Input 14
Active-Low Conversion Start Input
External Differential Reference Negative Input /Analog
Input 15
External Differential Reference Negative Input
Ground
External Positive Reference Input. Apply a reference
voltage at REF+. Bypass to GND with a 0.47FF
capacitor.
Power-Supply Input. Bypass to GND with a 10FF in
parallel with a 0.1FF capacitors.
Serial Clock Input. Clocks data in and out of the serial
interface
Active-Low Chip Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance or three-state.
Serial Data Input. DIN data is latched into the serial
interface on the rising edge of SCLK.
Digital I/O Ground
Interface Digital Power-Supply Input. Bypass to GND
with a 10FF in parallel with a 0.1FF capacitors.
Serial Data Output. Data is clocked out on the falling
edge of SCLK. When CS is high, DOUT is high
impedance or three-state.
End of Conversion Output. Data is valid after EOC pulls
low (Internal clock mode only).
Exposed Pad. Connect EP directly to GND plane for
guaranteed performance.
MAX11120–MAX11128
4-/8-/16-Channel ADCs
FUNCTION
Pin Description
16

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