MAX11127ATI+ Maxim Integrated, MAX11127ATI+ Datasheet
MAX11127ATI+
Specifications of MAX11127ATI+
Related parts for MAX11127ATI+
MAX11127ATI+ Summary of contents
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... MICROWIRE is a registered trademark of National Semiconductor Corporation. Ordering Information appears at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. MAX11120–MAX11128 4-/8-/16-Channel ADCs S Scan Modes, Internal Averaging, and Internal Clock ...
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... DYNAMIC PERFORMANCE (250kHz, input sine wave) (Notes 3 and 7) Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion (Up to the 5th Harmonic) Spurious-Free Dynamic Range Intermodulation Distortion Maxim Integrated Continuous Power Dissipation (T TQFN (derate 34.4mW/NC above +70NC)..................2758mW Operating Temperature Range ........................ -40NC to +125NC + 0.3V) and +4V DD Junction Temperature .....................................................+150NC Storage Temperature Range ...
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... ANALOG INPUT Input Voltage Range Absolute Input Voltage Range Static Input Leakage Current Input Capacitance EXTERNAL REFERENCE INPUT REF- Input Voltage Range REF+ Input Voltage Range REF+ Input Current Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS -3dB -0 ...
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... DIGITAL OUTPUTS (DOUT, EOC) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current Power Dissipation Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS V ...
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... DC ACCURACY (Notes 3 and 4) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Offset Error Temperature Coefficient Gain Temperature Coefficient Channel-to-Channel Offset Matching Line Rejection Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS t Externally clocked conversion CP ...
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... Acquisition Time Conversion Time External Clock Frequency Aperture Delay Aperture Jitter ANALOG INPUT Input Voltage Range Absolute Input Voltage Range Static Input Leakage Current Input Capacitance Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS SINAD SNR ...
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... DIGITAL OUTPUTS (DOUT, EOC) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current Power Dissipation Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS V ...
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... DC ACCURACY (Notes 3 and 4) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Offset Error Temperature Coefficient Gain Temperature Coefficient Channel-to-Channel Offset Matching Line Rejection Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS t Externally clocked conversion CP ...
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... Acquisition Time Conversion Time External Clock Frequency Aperture Delay Aperture Jitter ANALOG INPUT Input Voltage Range Absolute Input Voltage Range Static Input Leakage Current Input Capacitance Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS SINAD SNR ...
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... DIGITAL OUTPUTS (DOUT, EOC) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage Digital I/O Supply Voltage Positive Supply Current Power Dissipation Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL CONDITIONS V ...
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... OSC_TYP Note 9: The operational input voltage range for each individual input of a differentially configured pair is from V operational input voltage difference is from -V Note 10: See Figure 3 (Equivalent Input Circuit). Note 11: Guaranteed by characterization. Maxim Integrated = 1Msps 16MHz, 50% duty cycle, V SAMPLE SCLK = +25NC.) (Note 2) A SYMBOL ...
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... Figure 1. Detailed Serial-Interface Timing Diagram (MAX11122ATI+/MAX11125ATI+/MAX11128ATI+, T INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 1 1.0Msps SAMPLE 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 3072 DIGITAL OUTPUT CODE (DECIMAL) Maxim Integrated Typical Operating Characteristics = +25°C, unless otherwise noted.) A DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 1 1.0Msps SAMPLE 0.5 0 -0.5 -1.0 4096 0 1024 2048 DIGITAL OUTPUT CODE (DECIMAL) MAX11120– ...
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... THD vs. ANALOG INPUT FREQUENCY - 1.0Msps SAMPLE -85 -90 -95 -100 0 100 200 300 400 f (kHz) IN Maxim Integrated Typical Operating Characteristics (continued) = +25°C, unless otherwise noted.) A HISTOGRAM FOR 30,000 CONVERSIONS 35,000 f = 1Msps SAMPLE 30,000 29992 CODE HITS 25,000 20,000 15,000 10,000 5000 4 CODE HITS ...
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... FREQUENCY (kHz) ANALOG SUPPLY CURRENT vs. TEMPERATURE 3 1.0Msps SAMPLE V = 3.0V DD 2.5 2.0 1.5 1.0 -40 -25 - TEMPERATURE (°C) Maxim Integrated Typical Operating Characteristics (continued) = +25°C, unless otherwise noted -92.369dB HD3 f = 254.4kHz A = -104.1dB HD2 f = 500kHz 300 400 500 110 125 MAX11120–MAX11128 4-/8-/16-Channel ADCs REFERENCE CURRENT vs ...
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... Low-Power, Serial 12-/10-/8-Bit, TOP VIEW 21 20 DGND 22 OVDD 23 24 DOUT 25 EOC 26 AIN0 27 AIN1 + 28 AIN2 1 2 Maxim Integrated GND REF CNVST MAX11120 11 GND MAX11121 MAX11122 10 GND 9 GND 8 GND TQFN 4 CHANNEL DGND 22 OVDD 23 DOUT ...
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... Maxim Integrated MAX11120–MAX11128 4-/8-/16-Channel ADCs MAX11126 MAX11127 NAME MAX11128 (16 CHANNEL) 26, 27, 28, AIN0–AIN13 Analog Inputs 1–11 — AIN0–AIN7 Analog Inputs — AIN0–AIN3 Analog Inputs — GND ...
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... This feature frees the controlling unit for other tasks while lower- ing overall system noise and power consumption. The MAX11120–MAX11128 includes internal clock. The internal clock mode features an integrated FIFO, allowing Maxim Integrated MAX11120–MAX11128 4-/8-/16-Channel ADCs V OVDD ...
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... DOUT Ch[3] Ch[2] Ch[1] Ch[0] Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance Maxim Integrated MAX11120–MAX11128 Input Bandwidth Set CS low to latch input data at DIN on the rising edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK. A high-to-low transition on CS samples the analog inputs and initiates a new frame ...
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... GND (Figure 3). The MAX11120–MAX11128 feature 15 pseudo differen- tial inputs by setting the PDIFF_COM bits in the Unipolar register to 1 (Table 10). The 15 analog input signals inputs are referenced signal applied to the REF-/AIN15. Maxim Integrated single-ended REF REF+ ...
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... The MAX11120–MAX11128 operate from an internal oscillator, which is accurate within Q15% of the 13.33MHz nominal clock rate. Request internally timed conversions by writing the appropriate sequence to the ADC Mode Maxim Integrated OUTPUT CODE (hex -1.5 LSB Figure 5. Bipolar Transfer Function for 12-Bit Resolution ...
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... SCAN OPERATION AND RESULTS STORED IN FIFO Figure 6. Internal Conversions with CNVST CS EOC SCLK 1 DIN DOUT MODE CONTROL Figure 7. Internal Conversions with SWCNV Maxim Integrated 1 READ DATA FROM FIFO INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS 16 SWCNV = 1 INTERNAL OSCILLATOR ON SCAN OPERATION AND RESULTS STORED IN FIFO MAX11120– ...
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... Custom Scan0 or Custom Scan1 registers. A new CS DIN DOUT Figure 8. Echo Back the Configuration Data Maxim Integrated Analog Input I/P MUX is selected every frame on the thirteenth falling edge of SCLK. Custom_Int works with the internal clock. Custom_Ext works with the external clock. In Standard_Int and Standard_Ext modes, the device ...
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... T S Figure 9. SampleSet Use-Model Example Maxim Integrated the ADC can resolve (Nyquist Theorem) is 31.25kHz. If all 16 channels must be measured, with some chan- nels having greater than 31.25kHz input frequency, the user must revert back to manual mode requiring con- stant communication on the serial interface. SampleSet technology solves this problem ...
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... CHSEL[3:0] 10:7 0000 RESET[1:0] 6:5 Maxim Integrated Averaging Mode The MAX11120–MAX11128 communicate between the internal registers and the external circuitry through the SPI-/QSPI-compatible serial interface. register access and control. detail the various functions and configurations. For ADC mode control, set bit 15 of the register code identification to zero ...
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... Maxim Integrated Power Management Modes (Table 5). In external clock mode, PM[1:0] selects 00 between normal mode and various power-down modes of operation. External Clock Mode. Channel address is always present in internal clock mode. 0 Set to 1, DOUT is a 16-bit data word containing a 4-bit channel address, followed by a 12-bit conversion result led by the MSB ...
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... Maxim Integrated MODE NAME Scans channels 0 through N Clock mode: External clock 0 Standard_Ext Channel scan/sequence: N channels in ascending order Channel selection: See Table 4, CHSEL[3:0] determines channel N Averaging: No Scans channel N through the highest numbered channel. The FIFO stores X conversion results where Channel 16– ...
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... Maxim Integrated MODE NAME Scans preprogrammed channel sequence with maximum length of 256. There is no restriction on the channel pattern. Clock mode: External clock only 1 SampleSet Channel scan/sequence: Unique channel sequence Maximum depth: 256 conversions Channel Selection: See Table 4 Averaging: No Continue to operate in the previously selected mode ...
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... BIT NAME BIT CONFIG_SETUP 15:11 REFSEL 10 AVGON 9 Maxim Integrated Power-Down Mode When the PM_ bits in the ADC Mode Control register are asserted edge the next frame. The device powers up Static Shutdown again at the following falling edge of CS. There are two available options: (Table 6) ...
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... Low-Power, Serial 12-/10-/8-Bit, Table 6. ADC Configuration Register (continued) BIT NAME BIT NAVG[1:0] 8:7 NSCAN[1:0] 6:5 SPM[1:0] 4:3 ECHO 2 — 1:0 Maxim Integrated DEFAULT STATE Valid for internal clock mode only. AVGON NAVG1 Scans channel N and returns results. Valid for repeat mode only. ...
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... CHSEL[3:0] is used for STANDARD_EXT, STANDARD_INT, UPPER_INT modes of operation. CHSCAN[15:0] is used for CUSTOM_EXT and CUSTOM_INT modes of operation. Maxim Integrated DEFAULT STATE N/A Set to 10011 to select the RANGE register Set to 0 for AIN0/ Set to 1 for AIN0/1: +V Set to 0 for AIN2/ ...
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... CHANNEL SELECTION UNIPOLAR REGISTER BIT NAME UCH0 AIN0 Selection: 1 CHSEL[3:0] = 0000 CHSCAN0 = AIN1 Selection: 1 CHSEL[3:0] = 0001 CHSCAN1 = Maxim Integrated SUPPORTED WAVEFORMS REFSEL = 0 REF+ RANGE IN+ REF+ REF+ GND, AIN15 PDIFF_COM = 1 REF+ RANGE IN+ REF+ REF+ V ...
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... BCH10/11 5 BCH12/13 4 BCH14/15 3 — 2:0 Maxim Integrated STATE — Set to 10001 to select the Unipolar register. Set configure AIN0 and AIN1 for pseudo-differential conversion. 0 Set configure AIN0 and AIN1 for single-ended conversion. Set configure AIN2 and AIN3 for pseudo-differential conversion. ...
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... BIT NAME BIT DEFAULT STATE SMPL_SET 15:11 SEQ_LENGTH 10:3 — 2:0 Maxim Integrated — Set to 10100 to select the Custom Scan0 register. 0 Set scan AIN15. Set omit AIN15. 0 Set scan AIN14. Set omit AIN14. 0 Set scan AIN13. Set omit AIN13. ...
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... However, data on DOUT is not valid in following frames until a new ADC mode control instruction is coded. Programming Sequence Flow Chart See Figure 11 for programming sequence. Maxim Integrated MAX11120–MAX11128 4-/8-/16-Channel ADCs 16 1 ENTRY 1 ENTRY 2 ENTRY N = (SEQ_LENGTH) ...
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... BIPOLAR REGISTER SET PER REGISTER SET BIT PDIFF_COM CHANNEL UCH{X}/{X+ FOR PSEUDO- AND BCH{X}/{X+ FOR DIFFERENTIAL SELECTION SINGLE-ENDED SELECTION Figure 11. ADC Programming Sequence Maxim Integrated SELECT REFERENCE SINGLE-ENDED OR DIFFERENTIAL SELECT ADC FIGURE OUT NUMBER OF CHANNELS TO USE (N) FOR EACH ADC CHANNEL ...
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... ADC CONFIGURATION REGISTER YES UPPER-INT NO ADC CONFIGURATION REGISTER YES CUSTOM-INT NO ADC CONFIGURATION REGISTER Figure 12. ADC Mode Select Programming Sequence Maxim Integrated INTERNAL INTERNAL/EXTERNAL CLOCK NO AVERAGE YES SET AVG ON BIT TO 1 SET NAVG[1: ADC CONFIGURATION REGISTER SET NSCAN[1:0] FOR SCAN COUNT ...
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... 500I 4 5 INPUT 2 MAX4430 Figure 13. Typical Application Circuit Maxim Integrated U Initial voltage accuracy U Temperature drift U Current source capability U Current sink capability U Quiescent current U Noise. The MAX6033 and MAX6043 are also excellent +5V 0.1µF 10µ 100pF 0.1µF 10µF ...
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... Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Maxim Integrated MAX11120–MAX11128 4-/8-/16-Channel ADCs Definitions Total harmonic distortion (THD) is expressed as: ...
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... MAX11123ATI+ 28 TQFN-EP* MAX11124ATI+ 28 TQFN-EP* MAX11125ATI+ 28 TQFN-EP* MAX11126ATI+ 28 TQFN-EP* MAX11127ATI+ 28 TQFN-EP* MAX11128ATI+ 28 TQFN-EP* Note: All devices are specified over the -40°C to +125°C temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Package Information For the latest package outline information and land patterns (foot- prints www.maximintegrated.com/packages. Note that a “ ...
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... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...