LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 39

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

11.3 8-channel Data and 2-channel Data Support
• This selector configuration can process one system of 8-channel data and four systems of 2-channel data.
• The selector output is set with the MUXMOD, SW1SEL[2:0] and SW2SEL[2:0] registers.
• The 2-channel data is output from DATAOUT. This output can be muted with the DATAMUT register.
• The 8-channel data is output from DATAOUT and MPOUT[3:1]. This output can be muted with the D8CHMUT
• The S/PDIF signal can be output from MPOUT4. This is set with the RXTHR2[3:0] register.
• ERRF, MUTEB and NPCMF can output the MPIN4, MPIN5 and MPIN6 input signals according to the FLGERR and
• DSD data I/O is also possible. However, mute processing cannot be performed for both DSD channels.
• In the 8-channel data selector configuration, the MPOUT4 output is subject to the RXTHR2 register setting.
register.
FLGOUT register settings.
LRCKIN
DATAIN
MCKIN
MPIO1 26
MPIO2 27
MPIO3 28
MPIO4 29
BCKIN
MPIN1
MPIN2
MPIN3
MPIN4 10
MPIN5 11
MPIN6 12
RXIN8 56
RXIN7 57
RXIN6 58
RXIN5 59
(Input pins: MCKIN, BCKIN, LRCKIN, DATAIN, MPIN[3:1], MPIN[6:4], MPIO[4:1], RXIN[8:5])
(Output pins: MCKOUT, BCKOUT, LRCKOUT, DATAOUT, MPOUT[4:1], ERRF, MUTEB, NPCMF)
ADC
PLL
X’tal
DIR
3
4
5
6
7
8
9
Figure 11.3 8-channel Data and 2-channel Data Support Audio Selector Configuration
Master clock
Bit clock
LR clock
2ch data
Master clock
Bit clock
LR clock
2ch data
Master clock
Bit clock
LR clock
1,2/8ch data
3,4/8ch data
5,6/8ch data
7,8/8ch data
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
Error flag
Data mute
Non-PCM
(Clock & Data MUX: 7-bits×1 input, 4-bits×4 inputs, 7-bits×1 output)
“MPIN5P”
“MPIN6P”
“MPIN4P”
“MPSEL[1:0]”
Data mute flag from DIR
Non-PCM flag from DIR
PLL lock flag from DIR
4
4
4
4
7
LC89075W-H
“DIRERRP”
“DIRMUTP”
“DIRPCMP”
“SW1SEL[2:0]”
“SW2SEL[2:0]”
“D8CHMUT”
“MCKOUTP”
“MPO4MUT”
“FLGERR”
“FLGOUT”
1,2/8ch data || DSD
LR clock || DSD
“MUXMOD”
Master clock
3,4/8ch data
5,6/8ch data
7,8/8ch data
Data mute
S/PDIF
Error flag
Non-PCM
Bit clock
13
14
15
16
19
20
21
22
23
24
25
MCKOUT
BCKOUT
LRCKOUT
DATAOUT
MPOUT1
MPOUT2
MPOUT3
MPOUT4
ERRF
MUTEB
NPCMF
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