LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 24

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

10. Description of Digital Audio Interface Receiver (DIR)
10.1 Clocks
• When the PLL is unlocked, the DIR operates at the clock input to XIN. When the PLL is locked, the DIR operates at
10.1.1 PLL Source Master Clock
• The PLL synchronizes with the input S/PDIF and outputs a 512fs clock.
• The PLL clock is controlled by the RXCKAT, RXCKDV[1:0] and RXMCK[1:0] register settings.
• Normally, “RXCKAT=0” is set and a PLL clock is output for each input sampling frequency band. At this setting,
• When “RXCKAT=0” is set, the PLL clock is set by the RXCKDV[1:0] register
• To set an output clock that does not depend on the S/PDIF input sampling frequency, “RXCKAT=1” is set. At this
• When “RXCKAT=1” is set, the PLL clock is set by the RXMCK[1:0] register.
• When the PLL is locked, switching is not performed even when the RXCKAT, RXCKDV[1:0] and RXMCK[1:0]
• The PLL output clock setting flow is shown below. Note that the PLL can be stopped with the DIROPR register.
the internal VCO (PLL) clock.
output clock frequency fluctuation by varying the sampling frequency is kept to a narrow band, such as 512fs output
when fs=32kHz to 48kHz, 256fs output when fs=64kHz to 96kHz, and 128fs output when fs=128kHz to 192kHz.
setting, the clock frequency is always multiplied by a constant and output, such as output at 256fs for all sampling
frequencies from 32kHz to 192kHz.
registers setting are changed. These registers switching are executed when the PLL is in unlocked status. This setting
becomes valid after the PLL is locked again. And, only when "RXCKAT=1" is set, RXMCK[1:0] register can be
changed by setting "RXCKMU=1" even PLL lock state. However, the change is not reflected in MUTEB.
Lock detection
32k,44.1k,48k
Fs calculation
S/PDIF Input
“RXCKDV”
PLL output
“RXCKAT”
512fs
256fs
Fs=
0
Yes
01 or 11
Lock
1
00 or 10
Unlock
PLL output
No
512fs
*
PLL output
Free-run
Figure 10.1 PLL Output Clock Flow Diagram
64k,88.2k,96k
“RXCKDV”
PLL output
512fs
LC89075W-H
Fs=
Yes
10 or 11
*: When the RXFSLIM[1:0] register that limits
00 or 01
“RXMCK=00”: 256fs
“RXMCK=01”: 512fs
“RXMCK=10”: 128fs
PLL fixation output
PLL output
No
the input S/PDIF reception frequency is set
and data that exceeds this setting is judged, the
same processing is executed as when the PLL
is unlocked, and subsequent processing is not
performed. The clock source is automatically
switched to the XIN clock.
256fs
“RXCKMU”
0
128k,176.4k,192k
1
PLL output
128fs
Fs=
Yes
After locking PLL,
“RXMCK” can change
No
PLL output
256fs
No.A1858-24/69