LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 34

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

11. Description of Input/Output Audio Selector
• The LC89075W-H incorporates a peripheral circuit audio selector.
• The audio selector can select the following configurations.
11.1 2-channel Data Support
• This selector configuration can process six systems of 2-channel data. The output can use two separate systems.
• The selector output is set with the MUXMOD, SW1SEL[2:0] and SW2SEL[2:0] registers.
• Immediately after power-on, MCKOUT, BCKOUT, LRCKOUT and DATAOUT output the ADC or DIR block
• DATAOUT and MPOUT4 can be muted with the DATAMUT and MPO4MUT registers.
• The MPIN5 and MPIN6 input signals can be output from MUTEB and NPCMF with the FLGOUT register.
• DSD data I/O is also possible. However, mute processing cannot be performed for both DSD channels.
clocks and data according to the PLL status, and MPOUT[4:1] is set to “L” output.
1) 2-channel data support
2) 6-channel data and 2-channel data support
3) 8-channel data and 2-channel data support
LRCKIN
DATAIN
MCKIN
MPIO1 26
MPIO2 27
MPIO3 28
MPIO4 29
BCKIN
MPIN1
MPIN2
MPIN3
MPIN4 10
MPIN5 11
MPIN6 12
RXIN8 56
RXIN7 57
RXIN6 58
RXIN5 59
(Input pins: MCKIN, BCKIN, LRCKIN, DATAIN, MPIN[4:1], MPIO[4:1], RXIN[8:5])
(Output pins: MCKOUT, BCKOUT, LRCKOUT, DATAOUT, MPOUT[4:1], MUTEB, NPCMF)
ADC
X’tal
PLL
DIR
3
4
5
6
7
8
9
Master clock
Bit clock
LR clock
2ch data
Master clock
Bit clock
LR clock
2ch data
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
Master clock
Bit clock
LR clock || DSD
2ch data || DSD
Data mute
Non-PCM
Figure 11.1 2-channel Data Support Audio Selector Configuration
“MPIN5P”
“MPIN6P”
(Clock & Data MUX: 4-bits×6 inputs, 4-bits×2 outputs)
“MPSEL[1:0]”
Data mute flag from DIR
Non-PCM flag from DIR
4
4
4
4
4
4
LC89075W-H
(4-line input ×6, 4-line output ×2)
(6-line input ×1, 4-line input ×5, 6-line output ×1)
(7-line input ×1, 4-line input ×4, 7-line output ×1)
“DIRMUTP”
“DIRPCMP”
“SW1SEL[2:0]”
“SW2SEL[2:0]”
“MCKOUTP”
“MPO4MUT”
“DATAMUT”
“FLGOUT”
LR clock || DSD
2ch data || DSD
LR clock || DSD
2ch data || DSD
“MUXMOD”
Master clock
Master clock
Data mute
Non-PCM
Bit clock
Bit clock
S/PDIF
13
14
15
16
19
20
21
22
24
25
MCKOUT
BCKOUT
LRCKOUT
DATAOUT
MPOUT1
MPOUT2
MPOUT3
MPOUT4
MUTEB
NPCMF
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