LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 27

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

10.1.4 Mute Signal Output During the Clock Switching Period (MUTEB)
• MUTEB outputs a pulse when the output clocks change due to the PLL locked/unlocked status.
• The MUTEB pulse output polarity can be changed with the DIRMUTP register. The description below assumes that
• In the lock-in process, after input data is detected, MUTEB falls at the word clock generated from the XIN clock after
• In the unlock process, MUTEB falls at the same timing as the PLL lock detection signal ERRF, and then rises after
• Changes in the PLL locked status and the timing of clock changes can be seen by detecting the MUTEB pulse and
• The clocks switch after the PLL lock judgment, and this switching timing can be set with the RXCKWT[1:0] register.
• The clock output pins output free-running clocks immediately after the PLL is unlocked.
• In the unlock process, MUTEB is changed by ADBMOD register. See below for further details, “14. Microcontroller
DIRMUTP is 0.
the PLL is locked, and then rises at the same timing as ERRF once a certain period of time has passed.
the word clock generated from the XIN clock is counted for a certain number of times.
rising and falling edges.
At the initial setting, the clocks switch approximately 2.7ms after MUTEB falls. However, this value depends on the
condition that the oscillation amplifier is set to the constantly operating status. When set so that the oscillation
amplifier stops after the PLL is locked, the start-up time required until the oscillation amplifier stabilizes after the PLL
is unlocked is added to the value.
Interface”.
PLL locked status
PLL locked status
PLL clock
MCKOUT
PLL clock
MCKOUT
XIN clock
XIN clock
MUTEB
MUTEB
RXIN**
RXIN**
ERRF
ERRF
(DIRMUTP=0)
(DIRMUTP=0)
Digital data
UNLOCK
LOCK
XIN clock
Figure 10.3 Clock Switching Timing
PLL clock
(a) Lock-in stage
(b) Unlock stage
LC89075W-H
Digital data
Same timing as ERRF
After PLL lock
2.7ms**
3ms to 144ms
UNLOCK
****:
2.7ms**
LOCK
***:
**:
When set to
When set to
When set to
16384/fs ***
5.4ms ****
PLL clock
XIN clock
“
“
“
RXCKWT[1:0]=00
ADBMOD=0
ADBMOD=1
”
”
”
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