LUCL8567AAU-D AGERE [Agere Systems], LUCL8567AAU-D Datasheet - Page 37

• Manufacturer Part Number: LUCL8567AAU-D
• Description: SLIC for Peoples Republic of China Applications
• Manufacturer: AGERE [Agere Systems]

Data Sheet
August 1999
dc Applications
Latched Parallel Data Interface
The L8567 uses a latched parallel data control scheme
for both logic inputs and logic outputs. There is a latch
enable (EN) pin associated with this control scheme.
This data control scheme is designed to work in con-
junction with the quad T7507 codec. The T7507 codec
uses a serial data interface to receive and pass control
information to and from the controlling processor. The
T7507 controls the state of the L8567 SLIC via data
inputs and outputs corresponding to those of the L8567
SLIC. The T7507 also provides the EN control signal.
The T7507 is a quad codec; that is, four channels in a
single package. Each quad codec is designed to con-
trol the four corresponding L8567 SLIC devices. Control
inputs and outputs for the four channels are shared
among the four SLICs. For example, there is only one
B0 data output from the codec, and this control signal is
passed to the B0 control input on the four associated
SLICs. There are four EN outputs from the codec, one
to each SLIC. Data on the shared input or output leads
are valid to or from a given SLIC, depending on the
state of EN pin associated with the individual SLIC.
This is shown in Figure 29 below.
The control data inputs to the SLIC are B0 and B1,
which set the state of the SLIC and RD1I, RD2I, and
RD3I, which control the state of the EMR drivers. If an
Lucent Technologies Inc.
L8567-0
L8567-1
L8567-2
L8567-3
NSTAT
NSTAT
NSTAT
NSTAT
EN
EN
EN
EN
B0
B0
B0
B0
ENABLE
DATA INPUT
DATA OUTPUT
(continued)
Figure 29. Simplified Control Scheme
L7583 solid-state switch is used instead of EMRs, the
logic control outputs from the codec will go directly to
the state control inputs of the switch. In this mode of
operation, the relay drivers on the L8567 SLIC are not
used. If this is the case, tie the logic inputs RD1I, RD2I,
and RD3I to ground. This will force the drivers into the
not-active state, which is the state with the lowest
power consumption.
For the SLIC logic inputs, the latch is controlled by
input EN. When EN is high, the input data latches are
active; that is, data at the B0, B1, RD1I, RD2I, and
RD3I inputs are latched. The latched data will control
the state of the SLIC and drivers, and the SLIC and
drivers will not respond to changes at the logic inputs
while the level at EN is high. When EN is low, the input
data latch is not active; that is, data at the logic inputs
will flow through the latch and immediately determine
the state of the SLIC and drivers.
Logic outputs NSTAT and NTSD are also latched.
There is an internal pull-up associated with each of
these logic outputs. The operation of EN with the logic
outputs is slightly different from the operation of EN
with the logic inputs. In order for valid data to be at the
NSTAT and NTSD outputs, both the internal detector
(i.e., an off-hook or thermal shutdown condition,
respectively, exists) and pin EN must be low. Table 24
explains this.
People’s Republic of China Applications
EN0
EN1
EN2
EN3
B0C
NSTATc
T7507
CSEL
CCLK
D0
D1
DATA OUT
DATA IN
CHIP SELECT
CLOCK
L8567 SLIC for
SERIAL DATA
INTERFACE TO
CONTROLLER
12-3457(F)
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