HS9-82C37ARH-Q INTERSIL [Intersil Corporation], HS9-82C37ARH-Q Datasheet - Page 22

• Manufacturer Part Number: HS9-82C37ARH-Q
• Description: Radiation Hardened CMOS High Performance Programmable DMA Controller
• Manufacturer: INTERSIL [Intersil Corporation]

Rotating Priority
With Rotating Priority in a single chip DMA system, any
device requesting service is guaranteed to be recognized
after no more than three higher priority services have
occurred. This prevents any one channel from monopolizing
the system.
Regardless of which priority scheme is chosen, priority is
evaluated every time a HLDA is returned to the
HS-82C37ARH.
Compressed Timing - In order to achieve even greater
throughput where system characteristics permit, the HS-
82C37ARH can compress the transfer time to two clock
cycles. From Figure 4 it can be seen that state S3 is used to
extend the access time of the read pulse. By removing state
S3, the read pulse width is made equal to the write pulse
width and a transfer consists only of state S2 to change the
address and state S4 to perform the read/write. S1 states
will still occur when A8-A15 need updating (see Address
Generation). Timing for compressed transfers is found in
Figure 7. EOP will be output in S2 if compressed timing is
selected. Compressed Timing is not allowed for Memory-to-
Memory transfers.
Address Generation - In order to reduce pin count, the HS-
82C37ARH multiplexes the eight higher order address bits
on the data lines. State S1 is used to output the higher order
address bits to an external latch from which they may be
placed on the address bus. The falling edge of Address
Strobe (ADSTB) is used to load these bits from the data
lines to the latch. Address Enable (AEN) is used to enable
the bits onto the address bus through a three-state enable.
The lower order address bits are output by the HS-
82C37ARH directly. Lines A0-A7 should be connected to the
address bus. Figure 4 shows the time relationships between
CLK, AEN, ADSTB, DB0-DB7 and A0-A7.
During Block and Demand Transfer Mode service, which
include multiple transfers, the addresses generated will be
sequential. For many transfers the data held in the external
address latch will remain the same. This data need only
change when a carry or borrow from A7 to A8 takes place in
the normal sequence of addresses. To save time and speed
transfers, the HS-82C37ARH executes S1 states only when
updating of A8-A15 in the latch is necessary. This means for
long services, S1 states and Address Strobes may occur
only once every 256 transfers, a savings
cycles for each 256 transfers.
Highest 0
Lowest 3
Service
1sr
1
2
service
Service
2nd
2
3
0
1
service
request
Service
3rd
3
0
1
2
of 255 clock
HS-82C37ARH
service
939
Programming
The HS-82C37ARH will accept programming from the host
processor anytime that HLDA is inactive, and at least one
rising clock edge has occurred after HLDA went low. It is the
responsibility of the host to assure that programming and
HLDA are mutually exclusive.
Note that a problem can occur if a DMA request occurs on
an unmasked channel while the HS-82C37ARH is being pro-
grammed. For instance, the CPU may be starting to repro-
gram the two byte Address Register of channel 1 when
channel 1 receives a DMA request. If the HS-82C37ARH is
enabled (bit 2 in the command register is 0), and channel 1
is unmasked, a DMA service will occur after only one byte of
the Address Register has been reprogrammed. This condi-
tion can be avoided by disabling the controller (setting bit 2
in the Command Register) or masking the channel before
programming any of its registers. Once the programming is
complete, the controller can be enabled/unmasked.
After power-up it is suggested that all internal locations be
loaded with some known value, even if some channels are
unused. This will aid in debugging.
Register Description
Current Address Register - Each channel has a 16-bit Cur-
rent Address Register. This register holds the value of the
address used during DMA transfers. The address is auto-
matically incremented or decremented after each transfer
and the values of the address are stored in the Current
Address Register during the transfer. This register is written
or read by the microprocessor in successive 8-bit bytes. It
may also be reinitialized by an Autoinitialize back to its origi-
nal value. Autoinitialize takes place only after an EOP. In
Memory-to-Memory Mode, the channel 0 Current Address
Register can be prevented from incrementing or decrement-
ing by setting the address hold bit in the Command Register.
Current Word Register - Each channel has a 16-Bit Current
Word Count Register. This register determines the number
of transfers to be performed. The actual number of transfers
will be one more than the number programmed in the Cur-
rent Word Count Register (i.e., programming a count of 100
will result in 101 transfers). The word count is decremented
after each transfer. When the value in the register goes from
zero to FFFFH, a TC will be generated. This register is
loaded or read in successive 8-bit bytes by the microproces-
sor in the Program Condition. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC.
Base Address and Base Word Count Registers - Each
channel has a pair of Base Address and Base Word Count
Registers. These 16-bit registers store the original value of
their associated current registers. During Autoinitialization,
these values are used to restore the current registers to their
original values. The base registers are written simulta-
neously with their corresponding current register in 8-bit
bytes in the Program Condition by the microprocessor.
These registers cannot be read by the microprocessor.
Spec Number
518058