HS9-82C37ARH-Q INTERSIL [Intersil Corporation], HS9-82C37ARH-Q Datasheet - Page 19

• Manufacturer Part Number: HS9-82C37ARH-Q
• Description: Radiation Hardened CMOS High Performance Programmable DMA Controller
• Manufacturer: INTERSIL [Intersil Corporation]

Functional Description
The HS-82C37ARH Direct Memory Access Controller is
designed to improve the data transfer rate in systems which
must transfer data from an I/O device to memory, or move a
block of memory to an I/O device. It will also perform mem-
ory-to-memory block moves, or fill a block of memory with
data from a single location. Operating modes are provided to
handle single byte transfers as well as discontinuous data
streams, which allows the HS-82C37ARH to control data
movement with software transparency.
The DMA controller is a state-driven address and control sig-
nal generator, which permits data to be transferred directly
from an I/O device to memory or vice versa without ever
being stored in a temporary register. This can greatly
increase the data transfer rate for sequential operations,
compared with processor moves or repeated string instruc-
tions. Memory-to-Memory operations require temporary
internal storage of the data byte between generation of the
source and destination addresses, so Memory-to-Memory
transfers take place at less than half the rate of I/O opera-
tions, but still much faster than with central processor tech-
niques. The maximum data transfer rate obtainable with the
HS-82C37ARH is approximately 2.5 Mbytes/second, for an I/O
operation using the compressed timing option and 5MHz clock.
The block diagram of the HS-82C37ARH is shown on page
2. The Timing and Control Block, Priority Block, and internal
registers are the main components. Figure 8 lists the name
and size of the internal registers. The Timing and Control
Block derives internal timing from the CLOCK input, and
generates external control signals. The Priority Encoder
Block resolves priority contention between DMA channels
requesting service simultaneously.
DMA Operation
In a system, the HS-82C37ARH address and control outputs
and data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Register
Command Register
Temporary Register
Mode Registers
Mask Registers
Request Register
FIGURE 8 . HS-82C37ARH INTERNAL REGISTERS
NAME
16 Bits
16 Bits
16 bits
16 bits
16 bits
16 bits
8 bits
8 bits
8 bits
6 bits
4 bits
4 bits
SIZE
NUMBER
HS-82C37ARH
4
4
4
4
1
1
1
1
1
4
1
1
936
address byte. While inactive, the controller’s outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the HS-
82C37ARH drives the busses and generates the control sig-
nals to perform the data transfer. The operation performed
by activating one of the four DMA request inputs has previ-
ously been programmed into the controller via the Com-
mand, Mode, Address, and Word Count Registers.
For example, if a block of data is to be transferred from RAM
to an I/O device, the starting address of the data is loaded
into the HS-82C37ARH Current and Base Address Registers
for a particular channel, and the length of the block is loaded
into that channel’s Word Count Register. The corresponding
Mode Register is programmed for a Memory-to-I/O opera-
tion (read transfer), and various options are selected by the
Command Register and other Mode Register bits. The chan-
nel’s mask bit is cleared to enable recognition of a DMA
request (DREQ). The DREQ can either be a hardware signal
or a software command.
Once initiated, the block DMA transfer will proceed as the
controller outputs the data address, simultaneous MEMR
and IOW pulses, and selects an I/O device via the DMA
acknowledge (DACK) outputs. The data byte flows directly
from the RAM to the I/O device. After each byte is trans-
ferred, the address is automatically incremented (or decre-
mented) and the word count is decremented. The operation
is then repeated for the next byte. The controller stops trans-
ferring data when the Word Count Register underflows, or
an external EOP is applied.
To further understand HS-82C37ARH operation, the states
generated by each clock cycle must be considered. The
DMA controller operates in two major cycles, Active and Idle.
After being programmed, the controller is normally Idle until
a DMA request occurs on an unmasked channel, or a soft-
ware request is given. The HS-82C37ARH will then request
control of the system busses and enter the Active cycle. The
Active cycle is composed of several internal states, depend-
ing on what options have been selected and what type of
operation has been requested.
The HS-82C37ARH can assume seven separate states,
each composed of one full clock period. State I (SI) is the
Idle state. It is entered when the HS-82C37ARH has no valid
DMA requests pending, at the end of a transfer sequence, or
when a Reset or Master Clear has occurred. While in SI, the
DMA controller is inactive but may be in the Program Condi-
tion (being programmed by the processor.)
State 0 (S0) is the first state of a DMA service. The HS-
82C37ARH has requested a hold but the processor has not
yet returned an acknowledge. The HS-82C37ARH may still
be programmed until it has received HLDA from the CPU. An
acknowledge from the CPU will signal that DMA transfers
may begin. S1, S2, S3 and S4 are the working states of the
DMA service. If more time is needed to complete a transfer
than is available with normal timing, wait states (SW) can be
inserted between S2 or S3 and S4 by the use of the Ready
line on the HS-82C37ARH.
Spec Number
518058