HS9-82C37ARH-Q INTERSIL [Intersil Corporation], HS9-82C37ARH-Q Datasheet - Page 16

• Manufacturer Part Number: HS9-82C37ARH-Q
• Description: Radiation Hardened CMOS High Performance Programmable DMA Controller
• Manufacturer: INTERSIL [Intersil Corporation]

Burn-In Circuits
NOTES:
NOTES:
1. VDD = +6.0V
2. T
3. Resistors:
1. F0 is 50% duty cycle square wave pulse burst.
2. 1.0kHz
3. 10 cycles
4. F1 = Single pulse with width equal to 2 cycles of F0
5. F1 is left Low after pulse burst
6. F1 pulse occurs after start of F0 and ends before F0.
F0
F1
R1 = 10k
R2 = 2.7k
Input levels: 0.9VDD
A
= +125
F0
F1
F0
o
C Minimum
HS-82C37ARH 40 LEAD SBDIP
F0 Pulse Burst
10% (Pins 6, 7, 11-13, 17 - 20)
STATIC CONFIGURATION
5% (Pins 1, 2, 21-23, 24, 28-32, 34-39)
100kHz
5%
10
11
12
13
15
16
17
18
19
14
20
START-UP TIMING
1
2
3
4
5
6
7
8
9
VIH
1.0s
VDD, -0.3V
Part is Static Sensitive
Voltage Must be Ramped
F0 is left High after pulse burst
40
39
38
37
36
35
34
33
32
31
29
28
27
26
25
24
23
22
21
30
VIL
0.7V
VDD
HS-82C37ARH
933
NOTES:
F0
F0
F5
F1
F2
F3
F4
1. VDD = 6.5V
2. VDD = 6.0V
3. T
4. Part is Static Sensitive, Voltage Must be Ramped
5. Resistors:
R1 = 10k
R2 = 2.7k
A
= +125
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
o
NC
C Minimum
10% (Pins 6, 7, 11-13, 17 - 20)
10% (Pins 1, 2, 22-24, 28-32, 34-37, and LOADS)
5% (Burn-In)
5% (Life Test)
HS-82C37ARH 40 LEAD SBDIP
DYNAMIC CONFIGURATION
10
11
12
13
15
16
17
18
19
14
20
1
2
3
7
9
4
5
6
8
LOAD
VDD
2.7K
2.7K
Spec Number
40
39
38
37
36
35
34
33
25
24
23
22
21
32
31
30
29
28
27
26
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
VDD
F2
F1
F0
518058
F5
F4
F3