K4S161622D-TC/L55 SAMSUNG [Samsung semiconductor], K4S161622D-TC/L55 Datasheet - Page 6

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K4S161622D-TC/L55

Manufacturer Part Number
K4S161622D-TC/L55
Description
512K x 16Bit x 2 Banks Synchronous DRAM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
K4S161622D
AC CHARACTERISTICS
Note :
CLK cycle time
CLK to valid
output delay
Output data
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Also, supported tRDL=2CLK for - 55/60 part which is distinguished by bucket code "J".
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
From the next generation, tRDL will be only 2CLK for every clock frequency.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Parameter
Parameter
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
(AC operating conditions unless otherwise noted)
t
t
t
t
t
t
t
CC(min)
RRD(min)
RCD(min)
RP(min)
RAS(min)
RAS(max)
RC
Symbol
Symbol
t
t
t
(
t
t
t
SAC
t
t
t
SHZ
SLZ
CC
OH
CH
min
CL
SS
SH
)
Min
5.5
1.5
2
2
2
1
1
-
-
-
-
-
-
-
16.5
16.5
38.5
-55
5.5
11
55
-55
1000
Max
5
5
-
-
-
-
-
-
-
-
Min
2.5
2.5
2.5
1.5
-60
6
1
1
12
18
18
42
60
-
-
-
-
-
-
-
-
6
-60
1000
Max
5.5
5.5
-
-
-
-
-
-
-
-
Version
17.4
17.4
43.5
60.9
100
-70
14
1.75
Min
7
8.7
2.5
2.5
7
3
3
1
1
-
-
-
-
-70
1000
Max
5.5
7.7
5.5
7.7
-
-
-
-
-
-
-80
16
20
20
48
70
8
Min
2.5
10
8
3
3
2
1
1
-
-
-
-
-80
1000
Max
6
6
6
6
-
-
-
-
-
-
-10
10
20
20
20
48
70
CMOS SDRAM
Min
2.5
3.5
3.5
2.5
10
12
1
1
-
-
-
-
-10
Unit
1000
Max
ns
ns
ns
ns
ns
us
ns
6
8
6
8
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1, 2
1
2
3
3
3
3
2

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