ZL30105_05 ZARLINK [Zarlink Semiconductor Inc], ZL30105_05 Datasheet - Page 33

• Manufacturer Part Number: ZL30105_05
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.0
This section contains ZL30105 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
6.1
Jitter levels on the ZL30105 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30105 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
6.2
The ZL30105 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a
number of applicable oscillators and crystals that can be used with the ZL30105.
6.2.1
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30105, and the OSCo
output should be left open as shown in Figure 20.
Power Supply Decoupling
Master Clock
Applications
Clock Oscillator
1
2
3
4
Table 7 - Typical Clock Oscillator Specification
Frequency
Tolerance
Rise & fall time
Duty cycle
ZL30105
Figure 20 - Clock Oscillator Circuit
OSCo
Zarlink Semiconductor Inc.
OSCi
No Connection
ZL30105
33
20 MHz OUT
20 MHz
as required
< 10 ns
40% to 60%
+3.3 V
+3.3 V
GND
0.1 µF
Data Sheet