ZL30105_05 ZARLINK [Zarlink Semiconductor Inc], ZL30105_05 Datasheet - Page 27

• Manufacturer Part Number: ZL30105_05
• Description: T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTC TM and H.110
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.6
In general, clock redundancy implies that the redundant timing card DPLL tracks the output clock and/or frame
pulse of the active timing card DPLL. In case that the active timing card fails, the devices that use the active clock
and/or frame pulse must be able to switch to the redundant clock and/or frame pulse without experiencing
disruptions. Therefore the redundant signals must closely track the active signals. The ZL30105 supports this kind
of clock redundancy in various ways;
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•
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The method of clock redundancy shown in Figure 19 is that the redundant timing card is frequency and phase
locked to the active clock and frame pulse. The redundant card is configured as Secondary Master (SEC_MSTR=1)
and continuously adjusts the phase of its output clocks and frame pulses to match that of the active clock and frame
pulse. In this mode of operation, the bandwidth of the redundant timing card’s DPLL is much larger than that of the
active timing card’s DPLL, 922 Hz versus 1.8 Hz. Therefore the redundant clocks and frame pulses will track the
active clock and frame pulse closely even in the presence of the maximum tolerable input jitter and wander on the
active timing card’s reference input.
Lock only to the active clock. The ZL30105 uses the 922 Hz loop filter bandwidth to closely track the active
clock, even in the presence of jitter on the active clock. However the active and redundant frame pulse may
not be aligned.
Lock to the active frame pulse. Both the redundant clock and frame pulse will be aligned with the active clock
and frame pulse. However the ZL30105 loop filter bandwidth is limited to 14 Hz (2 kHz active frame pulse) or
58 Hz (8 kHz active frame pulse). Therefore the redundant clock and frame pulse will not track the active
frame pulse as closely in the presence of jitter on the active frame pulse as with a 922 Hz loop filter
bandwidth.
Lock to both the active clock and associated frame pulse. The ZL30105 uses the 922 Hz loop filter
bandwidth and thereby track the active clock and frame pulse in the presence of jitter on the active signals. It
will also align the redundant frame pulse with the active frame pulse.
Clock Redundancy Support
REF0
REF_OOR0
(internal signal)
REF_FAIL0
HOLDOVER
REF_SEL
LOCK
Note: This scenario is based on REF1 remaining good throughout the duration.
Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure
LOCK pin behaviour depends on phase and frequency offset of REF1.
Frequency Precision failure
10 to 20 s
REF0
Zarlink Semiconductor Inc.
REF1
ZL30105
27
Lock Time
Data Sheet